LXR uboot/include/configs/VOM405.h

   1/*
   2 * (C) Copyright 2001-2004
   3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
   4 *
   5 * SPDX-License-Identifier:     GPL-2.0+
   6 */
   7
   8/*
   9 * board/config.h - configuration options, board specific
  10 */
  11#ifndef __CONFIG_H
  12#define __CONFIG_H
  13
  14/*
  15 * High Level Configuration Options
  16 * (easy to change)
  17 */
  18#define CONFIG_405EP            1       /* This is a PPC405 CPU         */
  19#define CONFIG_VOM405           1       /* ...on a VOM405 board         */
  20
  21#define CONFIG_SYS_TEXT_BASE    0xFFFC8000
  22
  23#define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
  24
  25#define CONFIG_SYS_CLK_FREQ     33330000 /* external frequency to pll   */
  26
  27#undef  CONFIG_BOOTARGS
  28#undef  CONFIG_BOOTCOMMAND
  29
  30#define CONFIG_PREBOOT                  /* enable preboot variable      */
  31
  32#define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
  33
  34#undef  CONFIG_HAS_ETH1
  35
  36#define CONFIG_PPC4xx_EMAC
  37#define CONFIG_MII              1       /* MII PHY management           */
  38#define CONFIG_PHY_ADDR         0       /* PHY address                  */
  39#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
  40#define CONFIG_RESET_PHY_R      1       /* use reset_phy() to disable phy sleep mode */
  41
  42/*
  43 * BOOTP options
  44 */
  45#define CONFIG_BOOTP_SUBNETMASK
  46#define CONFIG_BOOTP_GATEWAY
  47#define CONFIG_BOOTP_HOSTNAME
  48#define CONFIG_BOOTP_BOOTPATH
  49#define CONFIG_BOOTP_DNS
  50#define CONFIG_BOOTP_DNS2
  51#define CONFIG_BOOTP_SEND_HOSTNAME
  52
  53/*
  54 * Command line configuration.
  55 */
  56#define CONFIG_CMD_IRQ
  57#define CONFIG_CMD_EEPROM
  58
  59#undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  60
  61#define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0    */
  62
  63#undef  CONFIG_PRAM                     /* no "protected RAM"           */
  64
  65/*
  66 * Miscellaneous configurable options
  67 */
  68#define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
  69
  70#if defined(CONFIG_CMD_KGDB)
  71#define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
  72#else
  73#define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
  74#endif
  75#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  76#define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
  77#define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
  78
  79#define CONFIG_SYS_DEVICE_NULLDEV       1       /* include nulldev device       */
  80
  81#define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
  82#define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM  */
  83
  84#define CONFIG_CONS_INDEX       1       /* Use UART0                    */
  85#define CONFIG_SYS_NS16550_SERIAL
  86#define CONFIG_SYS_NS16550_REG_SIZE     1
  87#define CONFIG_SYS_NS16550_CLK          get_serial_clock()
  88
  89#undef  CONFIG_SYS_EXT_SERIAL_CLOCK            /* no external serial clock used */
  90#define CONFIG_SYS_BASE_BAUD        691200
  91
  92/* The following table includes the supported baudrates */
  93#define CONFIG_SYS_BAUDRATE_TABLE       \
  94        { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
  95         57600, 115200, 230400, 460800, 921600 }
  96
  97#define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
  98#define CONFIG_SYS_EXTBDINFO    1               /* To use extended board_into (bd_t) */
  99
 100#define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 101
 102#define CONFIG_SYS_RX_ETH_BUFFER        16      /* use 16 rx buffer on 405 emac */
 103
 104/*
 105 * For booting Linux, the board info and command line data
 106 * have to be in the first 8 MB of memory, since this is
 107 * the maximum mapped by the Linux kernel during initialization.
 108 */
 109#define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 110/*
 111 * FLASH organization
 112 */
 113#define FLASH_BASE0_PRELIM      0xFFC00000      /* FLASH bank #0        */
 114
 115#define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 116#define CONFIG_SYS_MAX_FLASH_SECT       256     /* max number of sectors on one chip    */
 117
 118#define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 119#define CONFIG_SYS_FLASH_WRITE_TOUT     1000    /* Timeout for Flash Write (in ms)      */
 120
 121#define CONFIG_SYS_FLASH_WORD_SIZE      unsigned short  /* flash word size (width)      */
 122#define CONFIG_SYS_FLASH_ADDR0          0x5555  /* 1st address for flash config cycles  */
 123#define CONFIG_SYS_FLASH_ADDR1          0x2AAA  /* 2nd address for flash config cycles  */
 124/*
 125 * The following defines are added for buggy IOP480 byte interface.
 126 * All other boards should use the standard values (CPCI405 etc.)
 127 */
 128#define CONFIG_SYS_FLASH_READ0          0x0000  /* 0 is standard                        */
 129#define CONFIG_SYS_FLASH_READ1          0x0001  /* 1 is standard                        */
 130#define CONFIG_SYS_FLASH_READ2          0x0002  /* 2 is standard                        */
 131
 132#define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
 133
 134/*
 135 * Start addresses for the final memory configuration
 136 * (Set up by the startup code)
 137 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 138 */
 139#define CONFIG_SYS_SDRAM_BASE           0x00000000
 140#define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_MONITOR_BASE
 141#define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 142#define CONFIG_SYS_MONITOR_LEN          (~(CONFIG_SYS_TEXT_BASE) + 1)
 143#define CONFIG_SYS_MALLOC_LEN           (256 * 1024)
 144
 145#if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM)
 146# define CONFIG_SYS_RAMBOOT             1
 147#else
 148# undef CONFIG_SYS_RAMBOOT
 149#endif
 150
 151/*
 152 * Environment Variable setup
 153 */
 154#define CONFIG_ENV_IS_IN_EEPROM 1       /* use EEPROM for environment vars */
 155#define CONFIG_ENV_OFFSET               0x100   /* environment starts at the beginning of the EEPROM */
 156#define CONFIG_ENV_SIZE         0x700   /* 2048 bytes may be used for env vars*/
 157                                   /* total size of a CAT24WC16 is 2048 bytes */
 158
 159#define CONFIG_SYS_NVRAM_BASE_ADDR      0xF0000500              /* NVRAM base address   */
 160#define CONFIG_SYS_NVRAM_SIZE           242                     /* NVRAM size           */
 161
 162/*
 163 * I2C EEPROM (CAT24WC16) for environment
 164 */
 165#define CONFIG_SYS_I2C
 166#define CONFIG_SYS_I2C_PPC4XX
 167#define CONFIG_SYS_I2C_PPC4XX_CH0
 168#define CONFIG_SYS_I2C_PPC4XX_SPEED_0           400000
 169#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0           0x7F
 170
 171#define CONFIG_SYS_I2C_EEPROM_ADDR      0x50    /* EEPROM CAT28WC08             */
 172#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1        /* Bytes of address             */
 173/* mask of address bits that overflow into the "EEPROM chip address"    */
 174#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     0x07
 175#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4     /* The Catalyst CAT24WC08 has   */
 176                                        /* 16 byte page write mode using*/
 177                                        /* last 4 bits of the address   */
 178#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10   /* and takes up to 10 msec */
 179
 180/*
 181 * External Bus Controller (EBC) Setup
 182 */
 183#define CAN_BA          0xF0000000          /* CAN Base Address                 */
 184
 185/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization                       */
 186#define CONFIG_SYS_EBC_PB0AP            0x92015480
 187#define CONFIG_SYS_EBC_PB0CR            0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 188
 189/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization              */
 190#define CONFIG_SYS_EBC_PB2AP            0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 191#define CONFIG_SYS_EBC_PB2CR            0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
 192
 193/*
 194 * FPGA stuff
 195 */
 196#define CONFIG_SYS_XSVF_DEFAULT_ADDR    0xfffc0000
 197
 198/* FPGA program pin configuration */
 199#define CONFIG_SYS_FPGA_PRG             0x04000000  /* JTAG TMS pin (ppc output)     */
 200#define CONFIG_SYS_FPGA_CLK             0x02000000  /* JTAG TCK pin (ppc output)     */
 201#define CONFIG_SYS_FPGA_DATA            0x01000000  /* JTAG TDO->TDI data pin (ppc output) */
 202#define CONFIG_SYS_FPGA_INIT            0x00010000  /* unused (ppc input)            */
 203#define CONFIG_SYS_FPGA_DONE            0x00008000  /* JTAG TDI->TDO pin (ppc input) */
 204
 205/*
 206 * Definitions for initial stack pointer and data area (in data cache)
 207 */
 208/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
 209#define CONFIG_SYS_TEMP_STACK_OCM         1
 210
 211/* On Chip Memory location */
 212#define CONFIG_SYS_OCM_DATA_ADDR        0xF8000000
 213#define CONFIG_SYS_OCM_DATA_SIZE        0x1000
 214#define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM             */
 215#define CONFIG_SYS_INIT_RAM_SIZE        CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM    */
 216
 217#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 218#define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 219
 220/*
 221 * Definitions for GPIO setup (PPC405EP specific)
 222 *
 223 * GPIO0[0]     - External Bus Controller BLAST output
 224 * GPIO0[1-9]   - Instruction trace outputs -> GPIO
 225 * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
 226 * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
 227 * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
 228 * GPIO0[24-27] - UART0 control signal inputs/outputs
 229 * GPIO0[28-29] - UART1 data signal input/output
 230 * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
 231 */
 232/* GPIO Input:          OSR=00, ISR=00, TSR=00, TCR=0 */
 233/* GPIO Output:         OSR=00, ISR=00, TSR=00, TCR=1 */
 234/* Alt. Funtion Input:  OSR=00, ISR=01, TSR=00, TCR=0 */
 235/* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */
 236#define CONFIG_SYS_GPIO0_OSRL           0x40000500  /*  0 ... 15 */
 237#define CONFIG_SYS_GPIO0_OSRH           0x00000110  /* 16 ... 31 */
 238#define CONFIG_SYS_GPIO0_ISR1L          0x00000000  /*  0 ... 15 */
 239#define CONFIG_SYS_GPIO0_ISR1H          0x14000045  /* 16 ... 31 */
 240#define CONFIG_SYS_GPIO0_TSRL           0x00000000  /*  0 ... 15 */
 241#define CONFIG_SYS_GPIO0_TSRH           0x00000000  /* 16 ... 31 */
 242#define CONFIG_SYS_GPIO0_TCR            0xF7FE0014  /*  0 ... 31 */
 243
 244/*
 245 * Default speed selection (cpu_plb_opb_ebc) in mhz.
 246 * This value will be set if iic boot eprom is disabled.
 247 */
 248#define PLLMR0_DEFAULT   PLLMR0_133_66_66_33
 249#define PLLMR1_DEFAULT   PLLMR1_133_66_66_33
 250
 251#endif  /* __CONFIG_H */
 252