1/* 2 * (C) Copyright 2003-2005 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * (C) Copyright 2010 6 * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11#ifndef __CONFIG_H 12#define __CONFIG_H 13 14/* 15 * High Level Configuration Options 16 * (easy to change) 17 */ 18 19#define CONFIG_MPC5200 1 /* This is a MPC5200 CPU */ 20#define CONFIG_A4M072 1 /* ... on A4M072 board */ 21#define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */ 22 23#define CONFIG_SYS_TEXT_BASE 0xFE000000 24 25#define CONFIG_MISC_INIT_R 26 27#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ 28 29#define CONFIG_HIGH_BATS 1 /* High BATs supported */ 30 31/* 32 * Serial console configuration 33 */ 34#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ 35#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } 36/* define to enable silent console */ 37#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ 38 39/* 40 * PCI Mapping: 41 * 0x40000000 - 0x4fffffff - PCI Memory 42 * 0x50000000 - 0x50ffffff - PCI IO Space 43 */ 44 45#if defined(CONFIG_PCI) 46#define CONFIG_PCI_SCAN_SHOW 1 47#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 48 49#define CONFIG_PCI_MEM_BUS 0x40000000 50#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS 51#define CONFIG_PCI_MEM_SIZE 0x10000000 52 53#define CONFIG_PCI_IO_BUS 0x50000000 54#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS 55#define CONFIG_PCI_IO_SIZE 0x01000000 56#endif 57 58#define CONFIG_SYS_XLB_PIPELINING 1 59 60#undef CONFIG_EEPRO100 61 62/* USB */ 63#define CONFIG_USB_OHCI_NEW 64#define CONFIG_SYS_OHCI_BE_CONTROLLER 65#undef CONFIG_SYS_USB_OHCI_BOARD_INIT 66#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 67#define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB 68#define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200" 69#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 70 71#define CONFIG_TIMESTAMP /* Print image info with timestamp */ 72 73/* 74 * BOOTP options 75 */ 76#define CONFIG_BOOTP_BOOTFILESIZE 77#define CONFIG_BOOTP_BOOTPATH 78#define CONFIG_BOOTP_GATEWAY 79#define CONFIG_BOOTP_HOSTNAME 80 81/* 82 * Command line configuration. 83 */ 84#define CONFIG_CMD_EEPROM 85#define CONFIG_CMD_IDE 86 87#if defined(CONFIG_PCI) 88#define CONFIG_CMD_PCI 89#endif 90 91#if (CONFIG_SYS_TEXT_BASE == 0xFE000000) /* Boot low with 32 MB Flash */ 92#define CONFIG_SYS_LOWBOOT 1 93#define CONFIG_SYS_LOWBOOT32 1 94#endif 95 96/* 97 * Autobooting 98 */ 99 100#define CONFIG_SYS_AUTOLOAD "n" 101 102#undef CONFIG_BOOTARGS 103#define CONFIG_PREBOOT "run try_update" 104 105#define CONFIG_EXTRA_ENV_SETTINGS \ 106 "bk=run add_mtd ; run add_consolespec ; bootm 200000\0" \ 107 "cf1=diskboot 200000 0:1\0" \ 108 "bootcmd_cf1=run bcf1\0" \ 109 "bcf=setenv bootargs root=/dev/hda3\0" \ 110 "bootcmd_nfs=run bnfs\0" \ 111 "norargs=setenv bootargs root=/dev/mtdblock3 rootfstype=cramfs "\ 112 "panic=1\0" \ 113 "bootcmd_nor=cp.b ${kernel_addr} 200000 100000;" \ 114 "run norargs addip; run bk\0" \ 115 "bnfs=nfs 200000 ${rootpath}/boot/uImage;" \ 116 "run nfsargs addip ; run bk\0" \ 117 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 118 "nfsroot=${serverip}:${rootpath}\0" \ 119 "try_update=usb start;sleep 2;usb start;sleep 1;" \ 120 "fatload usb 0 2F0000 PCPUUPDT 2FF;usb stop;" \ 121 "source 2F0000\0" \ 122 "env_addr=FE060000\0" \ 123 "kernel_addr=FE100000\0" \ 124 "rootfs_addr=FE200000\0" \ 125 "add_mtd=setenv bootargs ${bootargs} mtdparts=" \ 126 "phys_mapped_flash:384k(u),640k(e),1m(k),30m(r)\0" \ 127 "bcf1=run cf1; run bcf; run addip; run bk\0" \ 128 "add_consolespec=setenv bootargs ${bootargs} " \ 129 "console=/dev/null quiet\0" \ 130 "addip=if test -n ${ethaddr};" \ 131 "then if test -n ${ipaddr};" \ 132 "then setenv bootargs ${bootargs} " \ 133 "ip=${ipaddr}:${serverip}:${gatewayip}:"\ 134 "${netmask}:${hostname}:${netdev}:off;" \ 135 "fi;" \ 136 "else;" \ 137 "setenv bootargs ${bootargs} no_ethaddr;" \ 138 "fi\0" \ 139 "hostname=CPUP0\0" \ 140 "netdev=eth0\0" \ 141 "bootcmd=run bootcmd_nor\0" \ 142 "" 143/* 144 * IPB Bus clocking configuration. 145 */ 146#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ 147 148/* 149 * I2C configuration 150 */ 151#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ 152#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */ 153 154#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ 155#define CONFIG_SYS_I2C_SLAVE 0x7F 156 157/* 158 * EEPROM configuration 159 */ 160#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* 1010010x */ 161#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 162#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 163#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 164#define CONFIG_SYS_EEPROM_WREN 1 165#define CONFIG_SYS_EEPROM_WP GPIO_PSC2_4 166 167/* 168 * Flash configuration 169 */ 170#define CONFIG_SYS_FLASH_BASE 0xFE000000 171#define CONFIG_SYS_FLASH_SIZE 0x02000000 172#if !defined(CONFIG_SYS_LOWBOOT) 173#error "CONFIG_SYS_LOWBOOT not defined?" 174#else /* CONFIG_SYS_LOWBOOT */ 175#if defined(CONFIG_SYS_LOWBOOT32) 176#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000) 177#endif 178#endif /* CONFIG_SYS_LOWBOOT */ 179 180#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ 181#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */ 182#define CONFIG_FLASH_CFI_DRIVER 183#define CONFIG_SYS_FLASH_CFI 184#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 185#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_CS0_START} 186#define CONFIG_SYS_FLASH_BANKS_SIZES {CONFIG_SYS_CS0_SIZE} 187 188/* 189 * Environment settings 190 */ 191#define CONFIG_ENV_IS_IN_FLASH 1 192#define CONFIG_ENV_SIZE 0x10000 193#define CONFIG_ENV_SECT_SIZE 0x20000 194#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 195#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 196 197#define CONFIG_ENV_OVERWRITE 1 198 199/* 200 * Memory map 201 */ 202#define CONFIG_SYS_MBAR 0xF0000000 203#define CONFIG_SYS_SDRAM_BASE 0x00000000 204#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 205 206/* Use SRAM until RAM will be available */ 207#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM 208#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */ 209 210#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 211#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 212 213#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 214#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 215# define CONFIG_SYS_RAMBOOT 1 216#endif 217 218#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */ 219#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 220#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 221 222/* 223 * Ethernet configuration 224 */ 225#define CONFIG_MPC5xxx_FEC 1 226#define CONFIG_MPC5xxx_FEC_MII100 227/* 228 * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb 229 */ 230/* #define CONFIG_MPC5xxx_FEC_MII10 */ 231#define CONFIG_PHY_ADDR 0x1f 232#define CONFIG_PHY_TYPE 0x79c874 /* AMD Phy Controller */ 233 234/* 235 * GPIO configuration 236 */ 237#define CONFIG_SYS_GPS_PORT_CONFIG 0x18000004 238 239/* 240 * Miscellaneous configurable options 241 */ 242#define CONFIG_CMDLINE_EDITING 1 243#define CONFIG_SYS_LONGHELP /* undef to save memory */ 244#if defined(CONFIG_CMD_KGDB) 245#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 246#else 247#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 248#endif 249#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 250#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 251#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 252 253#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ 254#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ 255 256#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 257 258#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ 259#if defined(CONFIG_CMD_KGDB) 260# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ 261#endif 262 263/* 264 * Various low-level settings 265 */ 266#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI 267#define CONFIG_SYS_HID0_FINAL HID0_ICE 268/* Flash at CSBoot, CS0 */ 269#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE 270#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE 271#define CONFIG_SYS_BOOTCS_CFG 0x0002DD00 272#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE 273#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE 274/* External SRAM at CS1 */ 275#define CONFIG_SYS_CS1_START 0x62000000 276#define CONFIG_SYS_CS1_SIZE 0x00400000 277#define CONFIG_SYS_CS1_CFG 0x00009930 278#define CONFIG_SYS_SRAM_BASE CONFIG_SYS_CS1_START 279#define CONFIG_SYS_SRAM_SIZE CONFIG_SYS_CS1_SIZE 280/* LED display at CS7 */ 281#define CONFIG_SYS_CS7_START 0x6a000000 282#define CONFIG_SYS_CS7_SIZE (64*1024) 283#define CONFIG_SYS_CS7_CFG 0x0000bf30 284 285#define CONFIG_SYS_CS_BURST 0x00000000 286#define CONFIG_SYS_CS_DEADCYCLE 0x33333003 287 288#define CONFIG_SYS_RESET_ADDRESS 0xff000000 289 290/*----------------------------------------------------------------------- 291 * USB stuff 292 *----------------------------------------------------------------------- 293 */ 294#define CONFIG_USB_CLOCK 0x0001BBBB 295#define CONFIG_USB_CONFIG 0x00001000 /* 0x4000 for SE mode */ 296 297/*----------------------------------------------------------------------- 298 * IDE/ATA stuff Supports IDE harddisk 299 *----------------------------------------------------------------------- 300 */ 301 302#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ 303 304#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ 305#undef CONFIG_IDE_LED /* LED for ide not supported */ 306 307#define CONFIG_IDE_PREINIT 308 309#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ 310#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 2 drives per IDE bus */ 311 312#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 313 314#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA 315 316/* Offset for data I/O */ 317#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) 318 319/* Offset for normal register accesses */ 320#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) 321 322/* Offset for alternate registers */ 323#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) 324 325/* Interval between registers */ 326#define CONFIG_SYS_ATA_STRIDE 4 327 328#define CONFIG_ATAPI 1 329 330/*----------------------------------------------------------------------- 331 * Open firmware flat tree support 332 *----------------------------------------------------------------------- 333 */ 334#define OF_CPU "PowerPC,5200@0" 335#define OF_SOC "soc5200@f0000000" 336#define OF_TBCLK (bd->bi_busfreq / 4) 337#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000" 338 339/* Support for the 7-segment display */ 340#define CONFIG_SYS_DISP_CHR_RAM CONFIG_SYS_CS7_START 341#define CONFIG_SHOW_ACTIVITY /* used for display realization */ 342 343#define CONFIG_SHOW_BOOT_PROGRESS 344 345#endif /* __CONFIG_H */ 346