LXR uboot/include/configs/am3517

   1/*
   2 * am3517_crane.h - Default configuration for AM3517 CraneBoard.
   3 *
   4 * Author: Srinath.R <srinath@mistralsolutions.com>
   5 *
   6 * Based on include/configs/am3517evm.h
   7 *
   8 * Copyright (C) 2011 Mistral Solutions pvt Ltd
   9 *
  10 * SPDX-License-Identifier:     GPL-2.0+
  11 */
  12
  13#ifndef __CONFIG_H
  14#define __CONFIG_H
  15
  16/*
  17 * High Level Configuration Options
  18 */
  19#define CONFIG_OMAP             1       /* in a TI OMAP core */
  20#define CONFIG_OMAP3_AM3517CRANE        1       /* working with CRANEBOARD */
  21
  22#define CONFIG_EMIF4    /* The chip has EMIF4 controller */
  23
  24#include <asm/arch/cpu.h>               /* get chip and board defs */
  25#include <asm/arch/omap.h>
  26
  27/* Clock Defines */
  28#define V_OSCK                  26000000        /* Clock output from T2 */
  29#define V_SCLK                  (V_OSCK >> 1)
  30
  31#define CONFIG_MISC_INIT_R
  32
  33#define CONFIG_CMDLINE_TAG              1       /* enable passing of ATAGs */
  34#define CONFIG_SETUP_MEMORY_TAGS        1
  35#define CONFIG_INITRD_TAG               1
  36#define CONFIG_REVISION_TAG             1
  37
  38/*
  39 * Size of malloc() pool
  40 */
  41#define CONFIG_ENV_SIZE                 (128 << 10)     /* 128 KiB sector */
  42#define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + (128 << 10))
  43                                                /* initial data */
  44/*
  45 * DDR related
  46 */
  47#define CONFIG_SYS_CS0_SIZE             (256 * 1024 * 1024)
  48
  49/*
  50 * Hardware drivers
  51 */
  52
  53/*
  54 * NS16550 Configuration
  55 */
  56#define V_NS16550_CLK                   48000000        /* 48MHz (APLL96/2) */
  57
  58#define CONFIG_SYS_NS16550_SERIAL
  59#define CONFIG_SYS_NS16550_REG_SIZE     (-4)
  60#define CONFIG_SYS_NS16550_CLK          V_NS16550_CLK
  61
  62/*
  63 * select serial console configuration
  64 */
  65#define CONFIG_CONS_INDEX               3
  66#define CONFIG_SYS_NS16550_COM3         OMAP34XX_UART3
  67#define CONFIG_SERIAL3                  3       /* UART3 on CRANEBOARD */
  68
  69/* allow to overwrite serial and ethaddr */
  70#define CONFIG_ENV_OVERWRITE
  71#define CONFIG_SYS_BAUDRATE_TABLE       {4800, 9600, 19200, 38400, 57600,\
  72                                        115200}
  73
  74/*
  75 * USB configuration
  76 * Enable CONFIG_USB_MUSB_HCD for Host functionalities MSC, keyboard
  77 * Enable CONFIG_USB_MUSB_UDC for Device functionalities.
  78 */
  79#define CONFIG_USB_AM35X                1
  80#define CONFIG_USB_MUSB_HCD                     1
  81
  82#ifdef CONFIG_USB_AM35X
  83
  84#ifdef CONFIG_USB_MUSB_HCD
  85
  86#ifdef CONFIG_USB_KEYBOARD
  87#define CONFIG_SYS_USB_EVENT_POLL
  88#define CONFIG_PREBOOT "usb start"
  89#endif /* CONFIG_USB_KEYBOARD */
  90
  91#endif /* CONFIG_USB_MUSB_HCD */
  92
  93#ifdef CONFIG_USB_MUSB_UDC
  94/* USB device configuration */
  95#define CONFIG_USB_DEVICE               1
  96#define CONFIG_USB_TTY                  1
  97/* Change these to suit your needs */
  98#define CONFIG_USBD_VENDORID            0x0451
  99#define CONFIG_USBD_PRODUCTID           0x5678
 100#define CONFIG_USBD_MANUFACTURER        "Texas Instruments"
 101#define CONFIG_USBD_PRODUCT_NAME        "AM3517CRANE"
 102#endif /* CONFIG_USB_MUSB_UDC */
 103
 104#endif /* CONFIG_USB_AM35X */
 105
 106/* commands to include */
 107#define CONFIG_CMD_JFFS2        /* JFFS2 Support                */
 108
 109#define CONFIG_CMD_NAND         /* NAND support                 */
 110
 111#define CONFIG_SYS_I2C
 112#define CONFIG_SYS_OMAP24_I2C_SPEED     100000
 113#define CONFIG_SYS_OMAP24_I2C_SLAVE     1
 114#define CONFIG_SYS_I2C_OMAP34XX
 115
 116/*
 117 * Board NAND Info.
 118 */
 119#define CONFIG_SYS_NAND_ADDR            NAND_BASE       /* physical address */
 120                                                        /* to access nand */
 121#define CONFIG_SYS_NAND_BASE            NAND_BASE       /* physical address */
 122                                                        /* to access */
 123                                                        /* nand at CS0 */
 124
 125#define CONFIG_SYS_MAX_NAND_DEVICE      1               /* Max number of */
 126                                                        /* NAND devices */
 127
 128#define CONFIG_JFFS2_NAND
 129/* nand device jffs2 lives on */
 130#define CONFIG_JFFS2_DEV                "nand0"
 131/* start of jffs2 partition */
 132#define CONFIG_JFFS2_PART_OFFSET        0x680000
 133#define CONFIG_JFFS2_PART_SIZE          0xf980000       /* sz of jffs2 part */
 134
 135/* Environment information */
 136
 137#define CONFIG_BOOTFILE         "uImage"
 138
 139#define CONFIG_EXTRA_ENV_SETTINGS \
 140        "loadaddr=0x82000000\0" \
 141        "console=ttyS2,115200n8\0" \
 142        "mmcdev=0\0" \
 143        "mmcargs=setenv bootargs console=${console} " \
 144                "root=/dev/mmcblk0p2 rw " \
 145                "rootfstype=ext3 rootwait\0" \
 146        "nandargs=setenv bootargs console=${console} " \
 147                "root=/dev/mtdblock4 rw " \
 148                "rootfstype=jffs2\0" \
 149        "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
 150        "bootscript=echo Running bootscript from mmc ...; " \
 151                "source ${loadaddr}\0" \
 152        "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
 153        "mmcboot=echo Booting from mmc ...; " \
 154                "run mmcargs; " \
 155                "bootm ${loadaddr}\0" \
 156        "nandboot=echo Booting from nand ...; " \
 157                "run nandargs; " \
 158                "nand read ${loadaddr} 280000 400000; " \
 159                "bootm ${loadaddr}\0" \
 160
 161#define CONFIG_BOOTCOMMAND \
 162        "mmc dev ${mmcdev}; if mmc rescan; then " \
 163                "if run loadbootscript; then " \
 164                        "run bootscript; " \
 165                "else " \
 166                        "if run loaduimage; then " \
 167                                "run mmcboot; " \
 168                        "else run nandboot; " \
 169                        "fi; " \
 170                "fi; " \
 171        "else run nandboot; fi"
 172
 173#define CONFIG_AUTO_COMPLETE    1
 174/*
 175 * Miscellaneous configurable options
 176 */
 177#define CONFIG_SYS_LONGHELP             /* undef to save memory */
 178#define CONFIG_SYS_CBSIZE               512     /* Console I/O Buffer Size */
 179/* Print Buffer Size */
 180#define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
 181                                        sizeof(CONFIG_SYS_PROMPT) + 16)
 182#define CONFIG_SYS_MAXARGS              32      /* max number of command */
 183                                                /* args */
 184/* Boot Argument Buffer Size */
 185#define CONFIG_SYS_BARGSIZE             (CONFIG_SYS_CBSIZE)
 186/* memtest works on */
 187#define CONFIG_SYS_MEMTEST_START        (OMAP34XX_SDRC_CS0)
 188#define CONFIG_SYS_MEMTEST_END          (OMAP34XX_SDRC_CS0 + \
 189                                        0x01F00000) /* 31MB */
 190
 191#define CONFIG_SYS_LOAD_ADDR            (OMAP34XX_SDRC_CS0) /* default load */
 192                                                                /* address */
 193
 194/*
 195 * AM3517 has 12 GP timers, they can be driven by the system clock
 196 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 197 * This rate is divided by a local divisor.
 198 */
 199#define CONFIG_SYS_TIMERBASE            OMAP34XX_GPT2
 200#define CONFIG_SYS_PTV                  2       /* Divisor: 2^(PTV+1) => 8 */
 201
 202/*-----------------------------------------------------------------------
 203 * Physical Memory Map
 204 */
 205#define CONFIG_NR_DRAM_BANKS    2       /* CS1 may or may not be populated */
 206#define PHYS_SDRAM_1            OMAP34XX_SDRC_CS0
 207#define PHYS_SDRAM_2            OMAP34XX_SDRC_CS1
 208
 209/*-----------------------------------------------------------------------
 210 * FLASH and environment organization
 211 */
 212
 213/* **** PISMO SUPPORT *** */
 214#define CONFIG_SYS_MAX_FLASH_SECT       520     /* max number of sectors */
 215                                                /* on one chip */
 216#define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max number of flash banks */
 217#define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 2 sectors */
 218
 219#define CONFIG_SYS_FLASH_BASE           NAND_BASE
 220
 221/* Monitor at start of flash */
 222#define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_FLASH_BASE
 223
 224#define CONFIG_NAND_OMAP_GPMC
 225#define CONFIG_ENV_IS_IN_NAND           1
 226#define SMNAND_ENV_OFFSET               0x260000 /* environment starts here */
 227
 228#define CONFIG_SYS_ENV_SECT_SIZE        (128 << 10)     /* 128 KiB sector */
 229#define CONFIG_ENV_OFFSET               SMNAND_ENV_OFFSET
 230#define CONFIG_ENV_ADDR                 SMNAND_ENV_OFFSET
 231
 232/*-----------------------------------------------------------------------
 233 * CFI FLASH driver setup
 234 */
 235/* timeout values are in ticks */
 236#define CONFIG_SYS_FLASH_ERASE_TOUT     (100 * CONFIG_SYS_HZ)
 237#define CONFIG_SYS_FLASH_WRITE_TOUT     (100 * CONFIG_SYS_HZ)
 238
 239/* Flash banks JFFS2 should use */
 240#define CONFIG_SYS_MAX_MTD_BANKS        (CONFIG_SYS_MAX_FLASH_BANKS + \
 241                                        CONFIG_SYS_MAX_NAND_DEVICE)
 242#define CONFIG_SYS_JFFS2_MEM_NAND
 243/* use flash_info[2] */
 244#define CONFIG_SYS_JFFS2_FIRST_BANK     CONFIG_SYS_MAX_FLASH_BANKS
 245#define CONFIG_SYS_JFFS2_NUM_BANKS      1
 246
 247#define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
 248#define CONFIG_SYS_INIT_RAM_ADDR        0x4020f800
 249#define CONFIG_SYS_INIT_RAM_SIZE        0x800
 250#define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_INIT_RAM_ADDR + \
 251                                         CONFIG_SYS_INIT_RAM_SIZE - \
 252                                         GENERATED_GBL_DATA_SIZE)
 253
 254/* Defines for SPL */
 255#define CONFIG_SPL_FRAMEWORK
 256#define CONFIG_SPL_BOARD_INIT
 257#define CONFIG_SPL_NAND_SIMPLE
 258#define CONFIG_SPL_TEXT_BASE            0x40200800
 259#define CONFIG_SPL_MAX_SIZE             (SRAM_SCRATCH_SPACE_ADDR - \
 260                                         CONFIG_SPL_TEXT_BASE)
 261
 262#define CONFIG_SPL_BSS_START_ADDR       0x80000000
 263#define CONFIG_SPL_BSS_MAX_SIZE         0x80000         /* 512 KB */
 264
 265#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION      1
 266#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
 267
 268#define CONFIG_SPL_NAND_BASE
 269#define CONFIG_SPL_NAND_DRIVERS
 270#define CONFIG_SPL_NAND_ECC
 271#define CONFIG_SPL_LDSCRIPT             "arch/arm/mach-omap2/u-boot-spl.lds"
 272
 273/* NAND boot config */
 274#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
 275#define CONFIG_SYS_NAND_5_ADDR_CYCLE
 276#define CONFIG_SYS_NAND_PAGE_COUNT      64
 277#define CONFIG_SYS_NAND_PAGE_SIZE       2048
 278#define CONFIG_SYS_NAND_OOBSIZE         64
 279#define CONFIG_SYS_NAND_BLOCK_SIZE      (128*1024)
 280#define CONFIG_SYS_NAND_BAD_BLOCK_POS   NAND_LARGE_BADBLOCK_POS
 281#define CONFIG_SYS_NAND_ECCPOS          {2, 3, 4, 5, 6, 7, 8, 9,\
 282                                                10, 11, 12, 13}
 283#define CONFIG_SYS_NAND_ECCSIZE         512
 284#define CONFIG_SYS_NAND_ECCBYTES        3
 285#define CONFIG_NAND_OMAP_ECCSCHEME      OMAP_ECC_HAM1_CODE_HW
 286#define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
 287#define CONFIG_SYS_NAND_U_BOOT_OFFS     0x80000
 288
 289/*
 290 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
 291 * 64 bytes before this address should be set aside for u-boot.img's
 292 * header. That is 0x800FFFC0--0x80100000 should not be used for any
 293 * other needs.
 294 */
 295#define CONFIG_SYS_TEXT_BASE            0x80100000
 296#define CONFIG_SYS_SPL_MALLOC_START     0x80208000
 297#define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
 298
 299#endif /* __CONFIG_H */
 300