LXR uboot/include/configs/atngw100mkii.h

   1/*
   2 * Copyright (C) 2006 Atmel Corporation
   3 *
   4 * Copyright (C) 2012 Andreas Bießmann <andreas@biessmann.org>
   5 *
   6 * Configuration settings for the AVR32 Network Gateway
   7 *
   8 * SPDX-License-Identifier:     GPL-2.0+
   9 */
  10#ifndef __CONFIG_H
  11#define __CONFIG_H
  12
  13#include <asm/arch/hardware.h>
  14
  15#define CONFIG_AT32AP
  16#define CONFIG_AT32AP7000
  17#define CONFIG_ATNGW100MKII
  18
  19#define CONFIG_BOARD_EARLY_INIT_R
  20
  21/*
  22 * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
  23 * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency
  24 * and the PBA bus to run at 1/4 the PLL frequency.
  25 */
  26#define CONFIG_PLL
  27#define CONFIG_SYS_POWER_MANAGER
  28#define CONFIG_SYS_OSC0_HZ              20000000
  29#define CONFIG_SYS_PLL0_DIV             1
  30#define CONFIG_SYS_PLL0_MUL             7
  31#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16
  32/*
  33 * Set the CPU running at:
  34 * PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz
  35 */
  36#define CONFIG_SYS_CLKDIV_CPU           0
  37/*
  38 * Set the HSB running at:
  39 * PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz
  40 */
  41#define CONFIG_SYS_CLKDIV_HSB           1
  42/*
  43 * Set the PBA running at:
  44 * PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz
  45 */
  46#define CONFIG_SYS_CLKDIV_PBA           2
  47/*
  48 * Set the PBB running at:
  49 * PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz
  50 */
  51#define CONFIG_SYS_CLKDIV_PBB           1
  52
  53/* Reserve VM regions for NOR flash, NAND flash and SDRAM */
  54#define CONFIG_SYS_NR_VM_REGIONS        3
  55
  56/*
  57 * The PLLOPT register controls the PLL like this:
  58 *   icp = PLLOPT<2>
  59 *   ivco = PLLOPT<1:0>
  60 *
  61 * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
  62 */
  63#define CONFIG_SYS_PLL0_OPT             0x04
  64
  65#define CONFIG_USART_BASE               ATMEL_BASE_USART1
  66#define CONFIG_USART_ID                 1
  67
  68/* User serviceable stuff */
  69
  70#define CONFIG_CMDLINE_TAG
  71#define CONFIG_SETUP_MEMORY_TAGS
  72#define CONFIG_INITRD_TAG
  73
  74#define CONFIG_BOOTARGS                                                 \
  75        "root=mtd:main rootfstype=jffs2"
  76#define CONFIG_BOOTCOMMAND                                              \
  77        "fsload 0x10400000 /uImage; bootm"
  78
  79
  80/*
  81 * After booting the board for the first time, new ethernet addresses
  82 * should be generated and assigned to the environment variables
  83 * "ethaddr" and "eth1addr". This is normally done during production.
  84 */
  85#define CONFIG_OVERWRITE_ETHADDR_ONCE
  86
  87/*
  88 * BOOTP/DHCP options
  89 */
  90#define CONFIG_BOOTP_SUBNETMASK
  91#define CONFIG_BOOTP_GATEWAY
  92
  93/*
  94 * Command line configuration.
  95 */
  96#define CONFIG_CMD_JFFS2
  97
  98#define CONFIG_ATMEL_USART
  99#define CONFIG_MACB
 100#define CONFIG_PORTMUX_PIO
 101#define CONFIG_SYS_NR_PIOS              5
 102#define CONFIG_SYS_HSDRAMC
 103#define CONFIG_GENERIC_ATMEL_MCI
 104#define CONFIG_ATMEL_SPI
 105
 106#define CONFIG_SYS_DCACHE_LINESZ        32
 107#define CONFIG_SYS_ICACHE_LINESZ        32
 108
 109#define CONFIG_NR_DRAM_BANKS            1
 110
 111#define CONFIG_SYS_FLASH_CFI
 112#define CONFIG_FLASH_CFI_DRIVER
 113#define CONFIG_SYS_FLASH_PROTECTION
 114
 115#define CONFIG_SYS_FLASH_BASE           0x00000000
 116#define CONFIG_SYS_FLASH_SIZE           0x800000
 117#define CONFIG_SYS_MAX_FLASH_BANKS      1
 118#define CONFIG_SYS_MAX_FLASH_SECT       135
 119
 120#define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_FLASH_BASE
 121#define CONFIG_SYS_TEXT_BASE            0x00000000
 122
 123#define CONFIG_SYS_INTRAM_BASE          INTERNAL_SRAM_BASE
 124#define CONFIG_SYS_INTRAM_SIZE          INTERNAL_SRAM_SIZE
 125#define CONFIG_SYS_SDRAM_BASE           EBI_SDRAM_BASE
 126
 127#define CONFIG_ENV_IS_IN_FLASH
 128#define CONFIG_ENV_SIZE                 65536
 129#define CONFIG_ENV_ADDR                 (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
 130
 131#define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
 132
 133#define CONFIG_SYS_MALLOC_LEN           (256*1024)
 134
 135/* Allow 4MB for the kernel run-time image */
 136#define CONFIG_SYS_LOAD_ADDR            (EBI_SDRAM_BASE + 0x00400000)
 137#define CONFIG_SYS_BOOTPARAMS_LEN       (16 * 1024)
 138
 139/* Other configuration settings that shouldn't have to change all that often */
 140#define CONFIG_SYS_CBSIZE               256
 141#define CONFIG_SYS_MAXARGS              16
 142#define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 143#define CONFIG_SYS_LONGHELP
 144
 145#define CONFIG_SYS_MEMTEST_START        CONFIG_SYS_SDRAM_BASE
 146#define CONFIG_SYS_MEMTEST_END          (CONFIG_SYS_MEMTEST_START + 0x1f00000)
 147
 148#define CONFIG_MTD_DEVICE
 149#define CONFIG_MTD_PARTITIONS
 150
 151#endif /* __CONFIG_H */
 152