uboot/include/configs/bur_am335x_common.h
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   1/*
   2 * bur_am335x_common.h
   3 *
   4 * common parts used by B&R AM335x based boards
   5 *
   6 * Copyright (C) 2016 Hannes Schmelzer <oe5hpm@oevsv.at> -
   7 * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
   8 *
   9 * SPDX-License-Identifier:        GPL-2.0+
  10 */
  11
  12#ifndef __BUR_AM335X_COMMON_H__
  13#define __BUR_AM335X_COMMON_H__
  14/* ------------------------------------------------------------------------- */
  15#define CONFIG_AM33XX
  16#define CONFIG_OMAP
  17#define CONFIG_MAX_RAM_BANK_SIZE        (1024 << 20)    /* 1GB */
  18
  19/* Timer information */
  20#define CONFIG_SYS_PTV                  2       /* Divisor: 2^(PTV+1) => 8 */
  21#define CONFIG_SYS_TIMERBASE            0x48040000      /* Use Timer2 */
  22#define CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC     /* enable 32kHz OSC at bootime */
  23#define CONFIG_POWER_TPS65217
  24
  25#include <asm/arch/omap.h>
  26
  27/* NS16550 Configuration */
  28#define CONFIG_SYS_NS16550_SERIAL
  29#define CONFIG_SYS_NS16550_REG_SIZE     (-4)
  30#define CONFIG_SYS_NS16550_CLK          48000000
  31#define CONFIG_SYS_NS16550_COM1         0x44e09000      /* UART0 */
  32
  33/* Network defines */
  34#define CONFIG_DRIVER_TI_CPSW           /* Driver for IP block */
  35#define CONFIG_MII                      /* Required in net/eth.c */
  36#define CONFIG_PHYLIB
  37#define CONFIG_PHY_NATSEMI
  38
  39/*
  40 * SPL related defines.  The Public RAM memory map the ROM defines the
  41 * area between 0x402F0400 and 0x4030B800 as a download area and
  42 * 0x4030B800 to 0x4030CE00 as a public stack area.  The ROM also
  43 * supports X-MODEM loading via UART, and we leverage this and then use
  44 * Y-MODEM to load u-boot.img, when booted over UART.  We must also include
  45 * the scratch space that U-Boot uses in SRAM.
  46 */
  47#define CONFIG_SPL_TEXT_BASE            0x402F0400
  48#define CONFIG_SPL_MAX_SIZE             (SRAM_SCRATCH_SPACE_ADDR - \
  49                                         CONFIG_SPL_TEXT_BASE)
  50
  51/*
  52 * Since SPL did pll and ddr initialization for us,
  53 * we don't need to do it twice.
  54 */
  55#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NOR_BOOT)
  56#define CONFIG_SKIP_LOWLEVEL_INIT
  57#endif /* !CONFIG_SPL_BUILD, ... */
  58/*
  59 * Our DDR memory always starts at 0x80000000 and U-Boot shall have
  60 * relocated itself to higher in memory by the time this value is used.
  61 */
  62#define CONFIG_SYS_LOAD_ADDR            0x80000000
  63/*
  64 * ----------------------------------------------------------------------------
  65 * DDR information.  We say (for simplicity) that we have 1 bank,
  66 * always, even when we have more.  We always start at 0x80000000,
  67 * and we place the initial stack pointer in our SRAM.
  68 */
  69#define CONFIG_NR_DRAM_BANKS            1
  70#define CONFIG_SYS_SDRAM_BASE           0x80000000
  71#define CONFIG_SYS_INIT_SP_ADDR         (NON_SECURE_SRAM_END - \
  72                                        GENERATED_GBL_DATA_SIZE)
  73
  74/* I2C */
  75#define CONFIG_SYS_I2C
  76#define CONFIG_SYS_OMAP24_I2C_SPEED     100000
  77#define CONFIG_SYS_OMAP24_I2C_SLAVE     1
  78#define CONFIG_SYS_I2C_OMAP24XX
  79/* GPIO */
  80#define CONFIG_OMAP_GPIO
  81
  82/*
  83 * Our platforms make use of SPL to initalize the hardware (primarily
  84 * memory) enough for full U-Boot to be loaded.  We also support Falcon
  85 * Mode so that the Linux kernel can be booted directly from SPL
  86 * instead, if desired.  We make use of the general SPL framework found
  87 * under common/spl/.  Given our generally common memory map, we set a
  88 * number of related defaults and sizes here.
  89 */
  90#define CONFIG_SPL_FRAMEWORK
  91/*
  92 * Place the image at the start of the ROM defined image space.
  93 * We limit our size to the ROM-defined downloaded image area, and use the
  94 * rest of the space for stack.  We load U-Boot itself into memory at
  95 * 0x80800000 for legacy reasons (to not conflict with older SPLs).  We
  96 * have our BSS be placed 1MiB after this, to allow for the default
  97 * Linux kernel address of 0x80008000 to work, in the Falcon Mode case.
  98 * We have the SPL malloc pool at the end of the BSS area.
  99 *
 100 * ----------------------------------------------------------------------------
 101 */
 102#undef  CONFIG_SYS_TEXT_BASE
 103#define CONFIG_SYS_TEXT_BASE            0x80800000
 104#define CONFIG_SPL_BSS_START_ADDR       0x80A00000
 105#define CONFIG_SPL_BSS_MAX_SIZE         0x80000         /* 512 KB */
 106#define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SPL_BSS_START_ADDR + \
 107                                        CONFIG_SPL_BSS_MAX_SIZE)
 108#define CONFIG_SYS_SPL_MALLOC_SIZE      CONFIG_SYS_MALLOC_LEN
 109
 110/* General parts of the framework, required. */
 111#define CONFIG_SPL_BOARD_INIT
 112#define CONFIG_SPL_LDSCRIPT             "arch/arm/mach-omap2/am33xx/u-boot-spl.lds"
 113
 114#endif  /* ! __BUR_AM335X_COMMON_H__ */
 115