LXR uboot/include/configs/canyonlands.h

   1/*
   2 * (C) Copyright 2008
   3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4 *
   5 * SPDX-License-Identifier:     GPL-2.0+
   6 */
   7
   8/************************************************************************
   9 * canyonlands.h - configuration for Canyonlands (460EX)
  10 ***********************************************************************/
  11#ifndef __CONFIG_H
  12#define __CONFIG_H
  13
  14#include <linux/kconfig.h>
  15
  16/*-----------------------------------------------------------------------
  17 * High Level Configuration Options
  18 *----------------------------------------------------------------------*/
  19/*
  20 * This config file is used for Canyonlands (460EX) Glacier (460GT)
  21 * and Arches dual (460GT)
  22 */
  23#ifdef CONFIG_CANYONLANDS
  24#define CONFIG_460EX                    /* Specific PPC460EX            */
  25#define CONFIG_HOSTNAME         canyonlands
  26#else
  27#define CONFIG_460GT                    /* Specific PPC460GT            */
  28#ifdef CONFIG_GLACIER
  29#define CONFIG_HOSTNAME         glacier
  30#else
  31#define CONFIG_HOSTNAME         arches
  32#define CONFIG_USE_NETDEV       eth1
  33#define CONFIG_BD_NUM_CPUS      2
  34#endif
  35#endif
  36
  37#define CONFIG_440
  38
  39#ifndef CONFIG_SYS_TEXT_BASE
  40#define CONFIG_SYS_TEXT_BASE    0xFFF80000
  41#endif
  42
  43/*
  44 * Include common defines/options for all AMCC eval boards
  45 */
  46#include "amcc-common.h"
  47
  48#define CONFIG_SYS_CLK_FREQ     66666667        /* external freq to pll */
  49
  50#define CONFIG_BOARD_EARLY_INIT_R               /* Call board_early_init_r */
  51#define CONFIG_MISC_INIT_R                      /* Call misc_init_r */
  52#define CONFIG_BOARD_TYPES                      /* support board types */
  53
  54/*-----------------------------------------------------------------------
  55 * Base addresses -- Note these are effective addresses where the
  56 * actual resources get mapped (not physical addresses)
  57 *----------------------------------------------------------------------*/
  58#define CONFIG_SYS_PCI_MEMBASE          0x80000000      /* mapped PCI memory    */
  59#define CONFIG_SYS_PCI_BASE             0xd0000000      /* internal PCI regs    */
  60#define CONFIG_SYS_PCI_TARGBASE CONFIG_SYS_PCI_MEMBASE
  61
  62#define CONFIG_SYS_PCIE_MEMBASE 0xb0000000      /* mapped PCIe memory   */
  63#define CONFIG_SYS_PCIE_MEMSIZE 0x08000000      /* smallest incr for PCIe port */
  64#define CONFIG_SYS_PCIE_BASE            0xc4000000      /* PCIe UTL regs */
  65
  66#define CONFIG_SYS_PCIE0_CFGBASE        0xc0000000
  67#define CONFIG_SYS_PCIE1_CFGBASE        0xc1000000
  68#define CONFIG_SYS_PCIE0_XCFGBASE       0xc3000000
  69#define CONFIG_SYS_PCIE1_XCFGBASE       0xc3001000
  70
  71/*
  72 * BCSR bits as defined in the Canyonlands board user manual.
  73 */
  74#define BCSR_USBCTRL_OTG_RST    0x32
  75#define BCSR_USBCTRL_HOST_RST   0x01
  76#define BCSR_SELECT_PCIE        0x10
  77
  78#define CONFIG_SYS_PCIE0_UTLBASE        0xc08010000ULL  /* 36bit physical addr  */
  79
  80/* base address of inbound PCIe window */
  81#define CONFIG_SYS_PCIE_INBOUND_BASE    0x000000000ULL  /* 36bit physical addr  */
  82
  83/* EBC stuff */
  84#if !defined(CONFIG_ARCHES)
  85#define CONFIG_SYS_BCSR_BASE            0xE1000000
  86#define CONFIG_SYS_FLASH_BASE           0xFC000000      /* later mapped to this addr */
  87#define CONFIG_SYS_FLASH_SIZE           (64 << 20)
  88#else
  89#define CONFIG_SYS_FPGA_BASE            0xE1000000
  90#define CONFIG_SYS_CPLD_ADDR            (CONFIG_SYS_FPGA_BASE + 0x00080000)
  91#define CONFIG_SYS_CPLD_DATA            (CONFIG_SYS_FPGA_BASE + 0x00080002)
  92#define CONFIG_SYS_FLASH_BASE           0xFE000000      /* later mapped to this addr  */
  93#define CONFIG_SYS_FLASH_SIZE           (32 << 20)
  94#endif
  95
  96#define CONFIG_SYS_NAND_ADDR            0xE0000000
  97#define CONFIG_SYS_BOOT_BASE_ADDR       0xFF000000      /* EBC Boot Space: 0xFF000000 */
  98#define CONFIG_SYS_FLASH_BASE_PHYS_H    0x4
  99#define CONFIG_SYS_FLASH_BASE_PHYS_L    0xCC000000
 100#define CONFIG_SYS_FLASH_BASE_PHYS      (((u64)CONFIG_SYS_FLASH_BASE_PHYS_H << 32) |    \
 101                                         (u64)CONFIG_SYS_FLASH_BASE_PHYS_L)
 102
 103#define CONFIG_SYS_OCM_BASE             0xE3000000      /* OCM: 64k             */
 104#define CONFIG_SYS_SRAM_BASE            0xE8000000      /* SRAM: 256k           */
 105#define CONFIG_SYS_SRAM_SIZE            (256 << 10)
 106#define CONFIG_SYS_LOCAL_CONF_REGS      0xEF000000
 107
 108#define CONFIG_SYS_AHB_BASE             0xE2000000      /* internal AHB peripherals     */
 109
 110/*-----------------------------------------------------------------------
 111 * Initial RAM & stack pointer (placed in OCM)
 112 *----------------------------------------------------------------------*/
 113#define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_BASE     /* OCM                  */
 114#define CONFIG_SYS_INIT_RAM_SIZE        (4 << 10)
 115#define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 116#define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 117
 118/*-----------------------------------------------------------------------
 119 * Serial Port
 120 *----------------------------------------------------------------------*/
 121#define CONFIG_CONS_INDEX       1       /* Use UART0                    */
 122
 123/*-----------------------------------------------------------------------
 124 * Environment
 125 *----------------------------------------------------------------------*/
 126/*
 127 * Define here the location of the environment variables (FLASH).
 128 */
 129#define CONFIG_ENV_IS_IN_FLASH  1       /* use FLASH for environment vars */
 130#define CONFIG_SYS_NOR_CS               0       /* NOR chip connected to CSx */
 131#define CONFIG_SYS_NAND_CS              3       /* NAND chip connected to CSx */
 132
 133/*-----------------------------------------------------------------------
 134 * FLASH related
 135 *----------------------------------------------------------------------*/
 136#define CONFIG_SYS_FLASH_CFI                    /* The flash is CFI compatible  */
 137#define CONFIG_FLASH_CFI_DRIVER         /* Use common CFI driver        */
 138#define CONFIG_SYS_FLASH_CFI_AMD_RESET  /* Use AMD (Spansion) reset cmd */
 139
 140#define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE}
 141#define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 142#define CONFIG_SYS_MAX_FLASH_SECT       512     /* max number of sectors on one chip    */
 143
 144#define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 145#define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 146
 147#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster)     */
 148#define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
 149
 150#ifdef CONFIG_ENV_IS_IN_FLASH
 151#define CONFIG_ENV_SECT_SIZE    0x20000         /* size of one complete sector  */
 152#define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 153#define CONFIG_ENV_SIZE         0x4000  /* Total Size of Environment Sector     */
 154
 155/* Address and size of Redundant Environment Sector     */
 156#define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
 157#define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 158#endif /* CONFIG_ENV_IS_IN_FLASH */
 159
 160/*-----------------------------------------------------------------------
 161 * NAND-FLASH related
 162 *----------------------------------------------------------------------*/
 163#define CONFIG_SYS_MAX_NAND_DEVICE      1
 164#define CONFIG_SYS_NAND_BASE            (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
 165#define CONFIG_SYS_NAND_SELECT_DEVICE  1        /* nand driver supports mutipl. chips   */
 166
 167/*------------------------------------------------------------------------------
 168 * DDR SDRAM
 169 *----------------------------------------------------------------------------*/
 170#if !defined(CONFIG_ARCHES)
 171/*
 172 * NAND booting U-Boot version uses a fixed initialization, since the whole
 173 * I2C SPD DIMM autodetection/calibration doesn't fit into the 4k of boot
 174 * code.
 175 */
 176#define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for setup     */
 177#define SPD_EEPROM_ADDRESS      {0x50, 0x51}    /* SPD i2c spd addresses*/
 178#define CONFIG_DDR_ECC                  /* with ECC support             */
 179#define CONFIG_DDR_RQDC_FIXED   0x80000038 /* fixed value for RQDC      */
 180
 181#else /* defined(CONFIG_ARCHES) */
 182
 183#define CONFIG_AUTOCALIB        "silent\0"      /* default is non-verbose    */
 184
 185#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION       /* IBM DDR autocalibration   */
 186#define DEBUG_PPC4xx_DDR_AUTOCALIBRATION        /* dynamic DDR autocal debug */
 187#undef CONFIG_PPC4xx_DDR_METHOD_A
 188
 189/* DDR1/2 SDRAM Device Control Register Data Values */
 190/* Memory Queue */
 191#define CONFIG_SYS_SDRAM_R0BAS          0x0000f000
 192#define CONFIG_SYS_SDRAM_R1BAS          0x00000000
 193#define CONFIG_SYS_SDRAM_R2BAS          0x00000000
 194#define CONFIG_SYS_SDRAM_R3BAS          0x00000000
 195#define CONFIG_SYS_SDRAM_PLBADDULL      0x00000000
 196#define CONFIG_SYS_SDRAM_PLBADDUHB      0x00000008
 197#define CONFIG_SYS_SDRAM_CONF1LL        0x00001080
 198#define CONFIG_SYS_SDRAM_CONF1HB        0x00001080
 199#define CONFIG_SYS_SDRAM_CONFPATHB      0x10a68000
 200
 201/* SDRAM Controller */
 202#define CONFIG_SYS_SDRAM0_MB0CF         0x00000701
 203#define CONFIG_SYS_SDRAM0_MB1CF         0x00000000
 204#define CONFIG_SYS_SDRAM0_MB2CF         0x00000000
 205#define CONFIG_SYS_SDRAM0_MB3CF         0x00000000
 206#define CONFIG_SYS_SDRAM0_MCOPT1        0x05322000
 207#define CONFIG_SYS_SDRAM0_MCOPT2        0x00000000
 208#define CONFIG_SYS_SDRAM0_MODT0         0x01000000
 209#define CONFIG_SYS_SDRAM0_MODT1         0x00000000
 210#define CONFIG_SYS_SDRAM0_MODT2         0x00000000
 211#define CONFIG_SYS_SDRAM0_MODT3         0x00000000
 212#define CONFIG_SYS_SDRAM0_CODT          0x00800021
 213#define CONFIG_SYS_SDRAM0_RTR           0x06180000
 214#define CONFIG_SYS_SDRAM0_INITPLR0      0xb5380000
 215#define CONFIG_SYS_SDRAM0_INITPLR1      0x82100400
 216#define CONFIG_SYS_SDRAM0_INITPLR2      0x80820000
 217#define CONFIG_SYS_SDRAM0_INITPLR3      0x80830000
 218#define CONFIG_SYS_SDRAM0_INITPLR4      0x80810040
 219#define CONFIG_SYS_SDRAM0_INITPLR5      0x80800532
 220#define CONFIG_SYS_SDRAM0_INITPLR6      0x82100400
 221#define CONFIG_SYS_SDRAM0_INITPLR7      0x8a080000
 222#define CONFIG_SYS_SDRAM0_INITPLR8      0x8a080000
 223#define CONFIG_SYS_SDRAM0_INITPLR9      0x8a080000
 224#define CONFIG_SYS_SDRAM0_INITPLR10     0x8a080000
 225#define CONFIG_SYS_SDRAM0_INITPLR11     0x80000432
 226#define CONFIG_SYS_SDRAM0_INITPLR12     0x808103c0
 227#define CONFIG_SYS_SDRAM0_INITPLR13     0x80810040
 228#define CONFIG_SYS_SDRAM0_INITPLR14     0x00000000
 229#define CONFIG_SYS_SDRAM0_INITPLR15     0x00000000
 230#define CONFIG_SYS_SDRAM0_RQDC          0x80000038
 231#define CONFIG_SYS_SDRAM0_RFDC          0x00000257
 232#define CONFIG_SYS_SDRAM0_RDCC          0x40000000
 233#define CONFIG_SYS_SDRAM0_DLCR          0x03000091
 234#define CONFIG_SYS_SDRAM0_CLKTR         0x40000000
 235#define CONFIG_SYS_SDRAM0_WRDTR         0x82000823
 236#define CONFIG_SYS_SDRAM0_SDTR1         0x80201000
 237#define CONFIG_SYS_SDRAM0_SDTR2         0x42204243
 238#define CONFIG_SYS_SDRAM0_SDTR3         0x090c0d1a
 239#define CONFIG_SYS_SDRAM0_MMODE         0x00000432
 240#define CONFIG_SYS_SDRAM0_MEMODE        0x00000004
 241#endif  /* !defined(CONFIG_ARCHES) */
 242
 243#define CONFIG_SYS_MBYTES_SDRAM 512     /* 512MB                        */
 244
 245/*-----------------------------------------------------------------------
 246 * I2C
 247 *----------------------------------------------------------------------*/
 248#define CONFIG_SYS_I2C_PPC4XX_SPEED_0           400000
 249
 250#define CONFIG_SYS_I2C_EEPROM_ADDR              (0xa8>>1)
 251#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 252#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 253#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10
 254
 255/* I2C bootstrap EEPROM */
 256#if defined(CONFIG_ARCHES)
 257#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR       0x54
 258#else
 259#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR       0x52
 260#endif
 261#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET     0
 262#define CONFIG_4xx_CONFIG_BLOCKSIZE             16
 263
 264/* I2C SYSMON (LM75, AD7414 is almost compatible)                       */
 265#define CONFIG_DTT_LM75                         /* ON Semi's LM75       */
 266#define CONFIG_DTT_AD7414                       /* use AD7414           */
 267#define CONFIG_DTT_SENSORS      {0}             /* Sensor addresses     */
 268#define CONFIG_SYS_DTT_MAX_TEMP 70
 269#define CONFIG_SYS_DTT_LOW_TEMP -30
 270#define CONFIG_SYS_DTT_HYSTERESIS       3
 271
 272#if defined(CONFIG_ARCHES)
 273#define CONFIG_SYS_I2C_DTT_ADDR 0x4a            /* AD7414 I2C address   */
 274#endif
 275
 276#if !defined(CONFIG_ARCHES)
 277/* RTC configuration */
 278#define CONFIG_RTC_M41T62
 279#define CONFIG_SYS_I2C_RTC_ADDR 0x68
 280#endif
 281
 282/*-----------------------------------------------------------------------
 283 * Ethernet
 284 *----------------------------------------------------------------------*/
 285#define CONFIG_IBM_EMAC4_V4
 286
 287#define CONFIG_HAS_ETH0
 288#define CONFIG_HAS_ETH1
 289
 290#if !defined(CONFIG_ARCHES)
 291#define CONFIG_PHY_ADDR         0       /* PHY address, See schematics  */
 292#define CONFIG_PHY1_ADDR        1
 293/* Only Glacier (460GT) has 4 EMAC interfaces */
 294#ifdef CONFIG_460GT
 295#define CONFIG_PHY2_ADDR        2
 296#define CONFIG_PHY3_ADDR        3
 297#define CONFIG_HAS_ETH2
 298#define CONFIG_HAS_ETH3
 299#endif
 300
 301#else /* defined(CONFIG_ARCHES) */
 302
 303#define CONFIG_FIXED_PHY        0xFFFFFFFF
 304#define CONFIG_PHY_ADDR         CONFIG_FIXED_PHY
 305#define CONFIG_PHY1_ADDR        0
 306#define CONFIG_PHY2_ADDR        1
 307#define CONFIG_HAS_ETH2
 308
 309#define CONFIG_SYS_FIXED_PHY_PORT(devnum, speed, duplex) \
 310                {devnum, speed, duplex}
 311#define CONFIG_SYS_FIXED_PHY_PORTS \
 312                CONFIG_SYS_FIXED_PHY_PORT(0, 1000, FULL)
 313
 314#define CONFIG_M88E1112_PHY
 315
 316/*
 317 * For the GPCS_PHYx_ADDR PHY address, choose some PHY address not
 318 * used by CONFIG_PHYx_ADDR
 319 */
 320#define CONFIG_GPCS_PHY_ADDR    0xA
 321#define CONFIG_GPCS_PHY1_ADDR   0xB
 322#define CONFIG_GPCS_PHY2_ADDR   0xC
 323#endif  /* !defined(CONFIG_ARCHES) */
 324
 325#define CONFIG_PHY_RESET                /* reset phy upon startup       */
 326#define CONFIG_PHY_GIGE                 /* Include GbE speed/duplex detection */
 327#define CONFIG_PHY_DYNAMIC_ANEG
 328
 329/*-----------------------------------------------------------------------
 330 * USB-OHCI
 331 *----------------------------------------------------------------------*/
 332/* Only Canyonlands (460EX) has USB */
 333#ifdef CONFIG_460EX
 334#define CONFIG_USB_OHCI_NEW
 335#undef CONFIG_SYS_OHCI_BE_CONTROLLER            /* 460EX has little endian descriptors  */
 336#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS /* 460EX has little endian register     */
 337#define CONFIG_SYS_OHCI_USE_NPS         /* force NoPowerSwitching mode          */
 338#define CONFIG_SYS_USB_OHCI_REGS_BASE   (CONFIG_SYS_AHB_BASE | 0xd0000)
 339#define CONFIG_SYS_USB_OHCI_SLOT_NAME   "ppc440"
 340#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
 341#define CONFIG_SYS_USB_OHCI_BOARD_INIT
 342#endif
 343
 344/*
 345 * Default environment variables
 346 */
 347#if !defined(CONFIG_ARCHES)
 348#define CONFIG_EXTRA_ENV_SETTINGS                                       \
 349        CONFIG_AMCC_DEF_ENV                                             \
 350        CONFIG_AMCC_DEF_ENV_POWERPC                                     \
 351        CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
 352        "kernel_addr=fc000000\0"                                        \
 353        "fdt_addr=fc1e0000\0"                                           \
 354        "ramdisk_addr=fc200000\0"                                       \
 355        "pciconfighost=1\0"                                             \
 356        "pcie_mode=RP:RP\0"                                             \
 357        ""
 358#else /* defined(CONFIG_ARCHES) */
 359#define CONFIG_EXTRA_ENV_SETTINGS                                       \
 360        CONFIG_AMCC_DEF_ENV                                             \
 361        CONFIG_AMCC_DEF_ENV_POWERPC                                     \
 362        CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
 363        "kernel_addr=fe000000\0"                                        \
 364        "fdt_addr=fe1e0000\0"                                           \
 365        "ramdisk_addr=fe200000\0"                                       \
 366        "pciconfighost=1\0"                                             \
 367        "pcie_mode=RP:RP\0"                                             \
 368        "ethprime=ppc_4xx_eth1\0"                                       \
 369        ""
 370#endif  /* !defined(CONFIG_ARCHES) */
 371
 372/*
 373 * Commands additional to the ones defined in amcc-common.h
 374 */
 375#if defined(CONFIG_ARCHES)
 376#define CONFIG_CMD_DTT
 377#define CONFIG_CMD_PCI
 378#define CONFIG_CMD_SDRAM
 379#elif defined(CONFIG_CANYONLANDS)
 380#define CONFIG_CMD_DTT
 381#define CONFIG_CMD_NAND
 382#define CONFIG_CMD_PCI
 383#define CONFIG_CMD_SATA
 384#define CONFIG_CMD_SDRAM
 385#elif defined(CONFIG_GLACIER)
 386#define CONFIG_CMD_DTT
 387#define CONFIG_CMD_NAND
 388#define CONFIG_CMD_PCI
 389#define CONFIG_CMD_SDRAM
 390#else
 391#error "board type not defined"
 392#endif
 393
 394/* Partitions */
 395
 396/*-----------------------------------------------------------------------
 397 * PCI stuff
 398 *----------------------------------------------------------------------*/
 399/* General PCI */
 400#define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 401#define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
 402#define CONFIG_PCI_CONFIG_HOST_BRIDGE
 403
 404/* Board-specific PCI */
 405#define CONFIG_SYS_PCI_TARGET_INIT              /* let board init pci target    */
 406#undef  CONFIG_SYS_PCI_MASTER_INIT
 407
 408#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014   /* IBM                          */
 409#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe   /* Whatever                     */
 410
 411#ifdef CONFIG_460GT
 412#if defined(CONFIG_ARCHES)
 413/*-----------------------------------------------------------------------
 414 * RapidIO I/O and Registers
 415 *----------------------------------------------------------------------*/
 416#define CONFIG_RAPIDIO
 417#define CONFIG_SYS_460GT_SRIO_ERRATA_1
 418
 419#define SRGPL0_REG_BAR          0x0000000DAA000000ull   /*  16MB */
 420#define SRGPL0_CFG_BAR          0x0000000DAB000000ull   /*  16MB */
 421#define SRGPL0_MNT_BAR          0x0000000DAC000000ull   /*  16MB */
 422#define SRGPL0_MSG_BAR          0x0000000DAD000000ull   /*  16MB */
 423#define SRGPL0_OUT_BAR          0x0000000DB0000000ull   /* 256MB */
 424
 425#define CONFIG_SYS_SRGPL0_REG_BAR       0xAA000000              /*  16MB */
 426#define CONFIG_SYS_SRGPL0_CFG_BAR       0xAB000000              /*  16MB */
 427#define CONFIG_SYS_SRGPL0_MNT_BAR       0xAC000000              /*  16MB */
 428#define CONFIG_SYS_SRGPL0_MSG_BAR       0xAD000000              /*  16MB */
 429
 430#define CONFIG_SYS_I2ODMA_BASE          0xCF000000
 431#define CONFIG_SYS_I2ODMA_PHYS_ADDR     0x0000000400100000ull
 432
 433#define CONFIG_PPC4XX_RAPIDIO_PROMISCUOUS_MODE
 434#undef CONFIG_PPC4XX_RAPIDIO_DEBUG
 435#undef CONFIG_PPC4XX_RAPIDIO_IN_BAR_USE_OCM
 436#define CONFIG_PPC4XX_RAPIDIO_USE_HB_PLB
 437#undef CONFIG_PPC4XX_RAPIDIO_LOOPBACK
 438#endif /* CONFIG_ARCHES */
 439#endif /* CONFIG_460GT */
 440
 441/*
 442 * SATA driver setup
 443 */
 444#ifdef CONFIG_CMD_SATA
 445#define CONFIG_SATA_DWC
 446#define CONFIG_LIBATA
 447#define SATA_BASE_ADDR          0xe20d1000      /* PPC460EX SATA Base Address */
 448#define SATA_DMA_REG_ADDR       0xe20d0800      /* PPC460EX SATA Base Address */
 449#define CONFIG_SYS_SATA_MAX_DEVICE      1       /* SATA MAX DEVICE */
 450/* Convert sectorsize to wordsize */
 451#define ATA_SECTOR_WORDS (ATA_SECT_SIZE/2)
 452#endif
 453
 454/*-----------------------------------------------------------------------
 455 * External Bus Controller (EBC) Setup
 456 *----------------------------------------------------------------------*/
 457
 458/*
 459 * Canyonlands has 64MBytes of NOR FLASH (Spansion 29GL512), but the
 460 * boot EBC mapping only supports a maximum of 16MBytes
 461 * (4.ff00.0000 - 4.ffff.ffff).
 462 * To solve this problem, the FLASH has to get remapped to another
 463 * EBC address which accepts bigger regions:
 464 *
 465 * 0xfc00.0000 -> 4.cc00.0000
 466 *
 467 * Arches has 32MBytes of NOR FLASH (Spansion 29GL256), it will be
 468 * remapped to:
 469 *
 470 * 0xfe00.0000 -> 4.ce00.0000
 471 */
 472
 473/* Memory Bank 0 (NOR-FLASH) initialization                                     */
 474#define CONFIG_SYS_EBC_PB0AP            0x10055e00
 475#define CONFIG_SYS_EBC_PB0CR            (CONFIG_SYS_BOOT_BASE_ADDR | 0x9a000)
 476
 477#if !defined(CONFIG_ARCHES)
 478/* Memory Bank 3 (NAND-FLASH) initialization                                            */
 479#define CONFIG_SYS_EBC_PB3AP            0x018003c0
 480#define CONFIG_SYS_EBC_PB3CR            (CONFIG_SYS_NAND_ADDR | 0x1E000) /* BAS=NAND,BS=1MB,BU=R/W,BW=32bit*/
 481#endif
 482
 483#if !defined(CONFIG_ARCHES)
 484/* Memory Bank 2 (CPLD) initialization                                          */
 485#define CONFIG_SYS_EBC_PB2AP            0x00804240
 486#define CONFIG_SYS_EBC_PB2CR            (CONFIG_SYS_BCSR_BASE | 0x18000) /* BAS=CPLD,BS=1M,BU=RW,BW=32bit */
 487
 488#else /* defined(CONFIG_ARCHES) */
 489
 490/* Memory Bank 1 (FPGA) initialization  */
 491#define CONFIG_SYS_EBC_PB1AP            0x7f8ffe80
 492#define CONFIG_SYS_EBC_PB1CR            (CONFIG_SYS_FPGA_BASE | 0x3a000) /* BAS=FPGA,BS=2MB,BU=R/W,BW=16bit*/
 493#endif  /* !defined(CONFIG_ARCHES) */
 494
 495#define CONFIG_SYS_EBC_CFG              0xbfc00000
 496
 497/*
 498 * Arches doesn't use PerCS3 but GPIO43, so let's configure the GPIO
 499 * pin multiplexing correctly
 500 */
 501#if defined(CONFIG_ARCHES)
 502#define GPIO43_USE              GPIO_SEL        /* On Arches this pin is used as GPIO */
 503#else
 504#define GPIO43_USE              GPIO_ALT1       /* On Glacier this pin is used as ALT1 -> PerCS3 */
 505#endif
 506
 507/*
 508 * PPC4xx GPIO Configuration
 509 */
 510#ifdef CONFIG_460EX
 511/* 460EX: Use USB configuration */
 512#define CONFIG_SYS_4xx_GPIO_TABLE { /*    Out             GPIO  Alternate1      Alternate2      Alternate3 */ \
 513{                                                                                       \
 514/* GPIO Core 0 */                                                                       \
 515{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 GMC1TxD(0)      USB2HostD(0)    */      \
 516{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 GMC1TxD(1)      USB2HostD(1)    */      \
 517{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 GMC1TxD(2)      USB2HostD(2)    */      \
 518{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 GMC1TxD(3)      USB2HostD(3)    */      \
 519{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 GMC1TxD(4)      USB2HostD(4)    */      \
 520{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 GMC1TxD(5)      USB2HostD(5)    */      \
 521{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 GMC1TxD(6)      USB2HostD(6)    */      \
 522{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 GMC1TxD(7)      USB2HostD(7)    */      \
 523{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 GMC1RxD(0)      USB2OTGD(0)     */      \
 524{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 GMC1RxD(1)      USB2OTGD(1)     */      \
 525{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 GMC1RxD(2)     USB2OTGD(2)     */      \
 526{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 GMC1RxD(3)     USB2OTGD(3)     */      \
 527{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO12 GMC1RxD(4)     USB2OTGD(4)     */      \
 528{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO13 GMC1RxD(5)     USB2OTGD(5)     */      \
 529{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO14 GMC1RxD(6)     USB2OTGD(6)     */      \
 530{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO15 GMC1RxD(7)     USB2OTGD(7)     */      \
 531{GPIO0_BASE, GPIO_IN , GPIO_SEL,  GPIO_OUT_0}, /* GPIO16 GMC1TxER       USB2HostStop    */      \
 532{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMC1CD         USB2HostNext    */      \
 533{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMC1RxER       USB2HostDir     */      \
 534{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO19 GMC1TxEN       USB2OTGStop     */      \
 535{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 GMC1CRS        USB2OTGNext     */      \
 536{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 GMC1RxDV       USB2OTGDir      */      \
 537{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO22 NFRDY                          */      \
 538{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 NFREN                          */      \
 539{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 NFWEN                          */      \
 540{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 NFCLE                          */      \
 541{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 NFALE                          */      \
 542{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO27 IRQ(0)                         */      \
 543{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO28 IRQ(1)                         */      \
 544{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO29 IRQ(2)                         */      \
 545{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO30 PerPar0        DMAReq2         IRQ(7)*/ \
 546{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO31 PerPar1        DMAAck2         IRQ(8)*/ \
 547},                                                                                      \
 548{                                                                                       \
 549/* GPIO Core 1 */                                                                       \
 550{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 PerPar2        EOT2/TC2        IRQ(9)*/ \
 551{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 PerPar3        DMAReq3         IRQ(4)*/ \
 552{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N    UART1_DSR_CTS_N UART2_SOUT*/ \
 553{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
 554{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N DMAAck3       UART3_SIN*/ \
 555{GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N    EOT3/TC3        UART3_SOUT*/ \
 556{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N    UART1_SOUT      */      \
 557{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N     UART1_SIN       */      \
 558{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 IRQ(3)                         */      \
 559{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 CS(1)                          */      \
 560{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 CS(2)                          */      \
 561{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 CS(3)          DMAReq1         IRQ(10)*/ \
 562{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO44 CS(4)          DMAAck1         IRQ(11)*/ \
 563{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5)          EOT/TC1         IRQ(12)*/ \
 564{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5)     DMAReq0         IRQ(13)*/ \
 565{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 PerAddr(6)     DMAAck0         IRQ(14)*/ \
 566{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 PerAddr(7)     EOT/TC0         IRQ(15)*/ \
 567{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49  Unselect via TraceSelect Bit  */      \
 568{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50  Unselect via TraceSelect Bit  */      \
 569{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51  Unselect via TraceSelect Bit  */      \
 570{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52  Unselect via TraceSelect Bit  */      \
 571{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53  Unselect via TraceSelect Bit  */      \
 572{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54  Unselect via TraceSelect Bit  */      \
 573{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55  Unselect via TraceSelect Bit  */      \
 574{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56  Unselect via TraceSelect Bit  */      \
 575{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57  Unselect via TraceSelect Bit  */      \
 576{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58  Unselect via TraceSelect Bit  */      \
 577{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59  Unselect via TraceSelect Bit  */      \
 578{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60  Unselect via TraceSelect Bit  */      \
 579{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61  Unselect via TraceSelect Bit  */      \
 580{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62  Unselect via TraceSelect Bit  */      \
 581{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63  Unselect via TraceSelect Bit  */      \
 582}                                                                                       \
 583}
 584#else
 585/* 460GT: Use EMAC2+3 configuration */
 586#define CONFIG_SYS_4xx_GPIO_TABLE { /*    Out             GPIO  Alternate1      Alternate2      Alternate3 */ \
 587{                                                                                       \
 588/* GPIO Core 0 */                                                                       \
 589{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 GMC1TxD(0)      USB2HostD(0)    */      \
 590{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 GMC1TxD(1)      USB2HostD(1)    */      \
 591{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 GMC1TxD(2)      USB2HostD(2)    */      \
 592{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 GMC1TxD(3)      USB2HostD(3)    */      \
 593{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 GMC1TxD(4)      USB2HostD(4)    */      \
 594{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 GMC1TxD(5)      USB2HostD(5)    */      \
 595{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 GMC1TxD(6)      USB2HostD(6)    */      \
 596{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 GMC1TxD(7)      USB2HostD(7)    */      \
 597{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 GMC1RxD(0)      USB2OTGD(0)     */      \
 598{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 GMC1RxD(1)      USB2OTGD(1)     */      \
 599{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 GMC1RxD(2)     USB2OTGD(2)     */      \
 600{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 GMC1RxD(3)     USB2OTGD(3)     */      \
 601{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO12 GMC1RxD(4)     USB2OTGD(4)     */      \
 602{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO13 GMC1RxD(5)     USB2OTGD(5)     */      \
 603{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO14 GMC1RxD(6)     USB2OTGD(6)     */      \
 604{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO15 GMC1RxD(7)     USB2OTGD(7)     */      \
 605{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMC1TxER       USB2HostStop    */      \
 606{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMC1CD         USB2HostNext    */      \
 607{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMC1RxER       USB2HostDir     */      \
 608{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMC1TxEN       USB2OTGStop     */      \
 609{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 GMC1CRS        USB2OTGNext     */      \
 610{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 GMC1RxDV       USB2OTGDir      */      \
 611{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO22 NFRDY                          */      \
 612{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 NFREN                          */      \
 613{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 NFWEN                          */      \
 614{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 NFCLE                          */      \
 615{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 NFALE                          */      \
 616{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO27 IRQ(0)                         */      \
 617{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO28 IRQ(1)                         */      \
 618{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO29 IRQ(2)                         */      \
 619{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO30 PerPar0        DMAReq2         IRQ(7)*/ \
 620{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO31 PerPar1        DMAAck2         IRQ(8)*/ \
 621},                                                                                      \
 622{                                                                                       \
 623/* GPIO Core 1 */                                                                       \
 624{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 PerPar2        EOT2/TC2        IRQ(9)*/ \
 625{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 PerPar3        DMAReq3         IRQ(4)*/ \
 626{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N    UART1_DSR_CTS_N UART2_SOUT*/ \
 627{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
 628{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N DMAAck3       UART3_SIN*/ \
 629{GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N    EOT3/TC3        UART3_SOUT*/ \
 630{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N    UART1_SOUT      */      \
 631{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N     UART1_SIN       */      \
 632{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 IRQ(3)                         */      \
 633{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 CS(1)                          */      \
 634{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 CS(2)                          */      \
 635{GPIO1_BASE, GPIO_OUT, GPIO43_USE, GPIO_OUT_0},/* GPIO43 CS(3)          DMAReq1         IRQ(10)*/ \
 636{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO44 CS(4)          DMAAck1         IRQ(11)*/ \
 637{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5)          EOT/TC1         IRQ(12)*/ \
 638{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5)     DMAReq0         IRQ(13)*/ \
 639{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 PerAddr(6)     DMAAck0         IRQ(14)*/ \
 640{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 PerAddr(7)     EOT/TC0         IRQ(15)*/ \
 641{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49  Unselect via TraceSelect Bit  */      \
 642{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50  Unselect via TraceSelect Bit  */      \
 643{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51  Unselect via TraceSelect Bit  */      \
 644{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52  Unselect via TraceSelect Bit  */      \
 645{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53  Unselect via TraceSelect Bit  */      \
 646{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54  Unselect via TraceSelect Bit  */      \
 647{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55  Unselect via TraceSelect Bit  */      \
 648{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56  Unselect via TraceSelect Bit  */      \
 649{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57  Unselect via TraceSelect Bit  */      \
 650{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58  Unselect via TraceSelect Bit  */      \
 651{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59  Unselect via TraceSelect Bit  */      \
 652{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60  Unselect via TraceSelect Bit  */      \
 653{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61  Unselect via TraceSelect Bit  */      \
 654{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62  Unselect via TraceSelect Bit  */      \
 655{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63  Unselect via TraceSelect Bit  */      \
 656}                                                                                       \
 657}
 658#endif
 659
 660#endif  /* __CONFIG_H */
 661