LXR uboot/include/configs/cm5200.h

   1/*
   2 * (C) Copyright 2003-2007
   3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4 *
   5 * SPDX-License-Identifier:     GPL-2.0+
   6 */
   7
   8#ifndef __CONFIG_H
   9#define __CONFIG_H
  10
  11/*
  12 * High Level Configuration Options
  13 */
  14#define CONFIG_MPC5200          1       /* This is an MPC5200 CPU */
  15#define CONFIG_CM5200           1       /* ... on CM5200 platform */
  16
  17#define CONFIG_SYS_TEXT_BASE    0xfc000000
  18
  19#define CONFIG_HIGH_BATS        1       /* High BATs supported */
  20
  21/*
  22 * Supported commands
  23 */
  24#define CONFIG_CMD_JFFS2
  25#define CONFIG_CMD_REGINFO
  26
  27/*
  28 * Serial console configuration
  29 */
  30#define CONFIG_PSC_CONSOLE      1       /* console is on PSC1 */
  31#define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200, 230400 }
  32
  33/*
  34 * Ethernet configuration
  35 */
  36#define CONFIG_MPC5xxx_FEC      1
  37#define CONFIG_MPC5xxx_FEC_MII100
  38#define CONFIG_PHY_ADDR         0x00
  39#define CONFIG_ENV_OVERWRITE    1       /* allow overwriting of ethaddr */
  40/* use misc_init_r() to read ethaddr from I2C EEPROM (see CONFIG_SYS_I2C_EEPROM) */
  41#define CONFIG_MISC_INIT_R      1
  42#define CONFIG_MAC_OFFSET       0x35    /* MAC address offset in I2C EEPROM */
  43
  44/*
  45 * POST support
  46 */
  47#define CONFIG_POST             (CONFIG_SYS_POST_MEMORY | CONFIG_SYS_POST_CPU | CONFIG_SYS_POST_I2C)
  48#define MPC5XXX_SRAM_POST_SIZE  (MPC5XXX_SRAM_SIZE - 4)
  49/* List of I2C addresses to be verified by POST */
  50#define CONFIG_SYS_POST_I2C_ADDRS       {CONFIG_SYS_I2C_SLAVE,  \
  51                                         CONFIG_SYS_I2C_IO,     \
  52                                         CONFIG_SYS_I2C_EEPROM}
  53
  54/* display image timestamps */
  55#define CONFIG_TIMESTAMP        1
  56
  57/*
  58 * Autobooting
  59 */
  60#define CONFIG_PREBOOT  "echo;" \
  61        "echo Type \"run net_nfs_fdt\" to mount root filesystem over NFS;" \
  62        "echo"
  63#undef CONFIG_BOOTARGS
  64
  65/*
  66 * Default environment settings
  67 */
  68#define CONFIG_EXTRA_ENV_SETTINGS                                       \
  69        "netdev=eth0\0"                                                 \
  70        "netmask=255.255.0.0\0"                                         \
  71        "ipaddr=192.168.160.33\0"                                       \
  72        "serverip=192.168.1.1\0"                                        \
  73        "gatewayip=192.168.1.1\0"                                       \
  74        "console=ttyPSC0\0"                                             \
  75        "u-boot_addr=100000\0"                                          \
  76        "kernel_addr=200000\0"                                          \
  77        "kernel_addr_flash=fc0c0000\0"                                  \
  78        "fdt_addr=400000\0"                                             \
  79        "fdt_addr_flash=fc0a0000\0"                                     \
  80        "ramdisk_addr=500000\0"                                         \
  81        "rootpath=/opt/eldk-4.1/ppc_6xx\0"                              \
  82        "u-boot=/tftpboot/cm5200/u-boot.bin\0"                          \
  83        "bootfile_fdt=/tftpboot/cm5200/uImage\0"                        \
  84        "fdt_file=/tftpboot/cm5200/cm5200.dtb\0"                        \
  85        "load=tftp ${u-boot_addr} ${u-boot}\0"                          \
  86        "update=prot off fc000000 +${filesize}; "                       \
  87                "era fc000000 +${filesize}; "                           \
  88                "cp.b ${u-boot_addr} fc000000 ${filesize}; "            \
  89                "prot on fc000000 +${filesize}\0"                       \
  90        "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
  91                "nfsroot=${serverip}:${rootpath}\0"                     \
  92        "flashargs=setenv bootargs root=/dev/mtdblock5 rw\0"            \
  93        "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"              \
  94        "addinit=setenv bootargs ${bootargs} init=/linuxrc\0"           \
  95        "addcons=setenv bootargs ${bootargs} "                          \
  96                "console=${console},${baudrate}\0"                      \
  97        "addip=setenv bootargs ${bootargs} "                            \
  98                "ip=${ipaddr}:${serverip}:${gatewayip}:"                \
  99                "${netmask}:${hostname}:${netdev}:off panic=1\0"        \
 100        "flash_flash=run flashargs addinit addip addcons;"              \
 101                "bootm ${kernel_addr_flash} - ${fdt_addr_flash}\0"      \
 102        "net_nfs_fdt=tftp ${kernel_addr} ${bootfile_fdt}; "             \
 103                "tftp ${fdt_addr} ${fdt_file}; run nfsargs addip "      \
 104                "addcons; bootm ${kernel_addr} - ${fdt_addr}\0"         \
 105        ""
 106#define CONFIG_BOOTCOMMAND      "run flash_flash"
 107
 108/*
 109 * Low level configuration
 110 */
 111
 112/*
 113 * Clock configuration
 114 */
 115#define CONFIG_SYS_MPC5XXX_CLKIN        33000000        /* SYS_XTAL_IN = 33MHz */
 116#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK 1       /* IPB = 133MHz */
 117
 118/*
 119 * Memory map
 120 */
 121#define CONFIG_SYS_MBAR         0xF0000000
 122#define CONFIG_SYS_SDRAM_BASE           0x00000000
 123#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
 124
 125#define CONFIG_SYS_LOWBOOT              1
 126
 127/* Use ON-Chip SRAM until RAM will be available */
 128#define CONFIG_SYS_INIT_RAM_ADDR        MPC5XXX_SRAM
 129#ifdef CONFIG_POST
 130/* preserve space for the post_word at end of on-chip SRAM */
 131#define CONFIG_SYS_INIT_RAM_SIZE        MPC5XXX_SRAM_POST_SIZE
 132#else
 133#define CONFIG_SYS_INIT_RAM_SIZE        MPC5XXX_SRAM_SIZE
 134#endif
 135
 136#define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 137#define CONFIG_BOARD_TYPES      1       /* we use board_type */
 138
 139#define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 140
 141#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 142#define CONFIG_SYS_MONITOR_LEN          (384 << 10)     /* 384 kB for Monitor */
 143#define CONFIG_SYS_MALLOC_LEN           (256 << 10)     /* 256 kB for malloc() */
 144#define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* initial mem map for Linux */
 145
 146/*
 147 * Flash configuration
 148 */
 149#define CONFIG_SYS_FLASH_CFI            1
 150#define CONFIG_FLASH_CFI_DRIVER 1
 151#define CONFIG_SYS_FLASH_BASE           0xfc000000
 152/* we need these despite using CFI */
 153#define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of flash banks */
 154#define CONFIG_SYS_MAX_FLASH_SECT       256     /* max num of sectors on one chip */
 155#define CONFIG_SYS_FLASH_SIZE           0x02000000 /* 32 MiB */
 156
 157#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 158#define CONFIG_SYS_RAMBOOT              1
 159#undef CONFIG_SYS_LOWBOOT
 160#endif
 161
 162/*
 163 * Chip selects configuration
 164 */
 165/* Boot Chipselect */
 166#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
 167#define CONFIG_SYS_BOOTCS_SIZE          CONFIG_SYS_FLASH_SIZE
 168#define CONFIG_SYS_BOOTCS_CFG           0x00087D31      /* for pci_clk = 33 MHz */
 169/* use board_early_init_r to enable flash write in CS_BOOT */
 170#define CONFIG_BOARD_EARLY_INIT_R
 171
 172/* Flash memory addressing */
 173#define CONFIG_SYS_CS0_START            CONFIG_SYS_FLASH_BASE
 174#define CONFIG_SYS_CS0_SIZE             CONFIG_SYS_FLASH_SIZE
 175
 176/* No burst, dead cycle = 1 for CS0 (Flash) */
 177#define CONFIG_SYS_CS_BURST             0x00000000
 178#define CONFIG_SYS_CS_DEADCYCLE 0x00000001
 179
 180/*
 181 * SDRAM configuration
 182 * settings for k4s561632E-xx75, assuming XLB = 132 MHz
 183 */
 184#define SDRAM_MODE      0x00CD0000      /* CASL 3, burst length 8 */
 185#define SDRAM_CONTROL   0x514F0000
 186#define SDRAM_CONFIG1   0xE2333900
 187#define SDRAM_CONFIG2   0x8EE70000
 188
 189/*
 190 * MTD configuration
 191 */
 192#define CONFIG_CMD_MTDPARTS     1
 193#define CONFIG_MTD_DEVICE               /* needed for mtdparts commands */
 194#define CONFIG_FLASH_CFI_MTD
 195#define MTDIDS_DEFAULT          "nor0=cm5200-0"
 196#define MTDPARTS_DEFAULT        "mtdparts=cm5200-0:"                    \
 197                                        "384k(uboot),128k(env),"        \
 198                                        "128k(redund_env),128k(dtb),"   \
 199                                        "2m(kernel),27904k(rootfs),"    \
 200                                        "-(config)"
 201
 202/*
 203 * I2C configuration
 204 */
 205#define CONFIG_HARD_I2C         1       /* I2C with hardware support */
 206#define CONFIG_SYS_I2C_MODULE           2       /* Select I2C module #2 */
 207#define CONFIG_SYS_I2C_SPEED            40000   /* 40 kHz */
 208#define CONFIG_SYS_I2C_SLAVE            0x0
 209#define CONFIG_SYS_I2C_IO               0x38    /* PCA9554AD I2C I/O port address */
 210#define CONFIG_SYS_I2C_EEPROM           0x53    /* I2C EEPROM device address */
 211
 212/*
 213 * RTC configuration
 214 */
 215#define CONFIG_RTC_MPC5200      1       /* use internal MPC5200 RTC */
 216
 217/*
 218 * USB configuration
 219 */
 220#define CONFIG_USB_OHCI         1
 221#define CONFIG_USB_CLOCK        0x0001BBBB
 222#define CONFIG_USB_CONFIG       0x00001000
 223/* Partitions (for USB) */
 224
 225/*
 226 * Invoke our last_stage_init function - needed by fwupdate
 227 */
 228#define CONFIG_LAST_STAGE_INIT  1
 229
 230/*
 231 * Environment settings
 232 */
 233#define CONFIG_ENV_IS_IN_FLASH  1
 234#define CONFIG_ENV_SIZE         0x10000
 235#define CONFIG_ENV_SECT_SIZE    0x20000
 236#define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
 237/* Configuration of redundant environment */
 238#define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 239#define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 240
 241/*
 242 * Pin multiplexing configuration
 243 */
 244
 245/*
 246 * CS1/GPIO_WKUP_6: GPIO (default)
 247 * ALTs: CAN1 on I2C1, CAN2 on TIMER0/1
 248 * IRDA/PSC6: UART
 249 * Ether: Ethernet 100Mbit with MD
 250 * PCI_DIS: PCI controller disabled
 251 * USB: USB
 252 * PSC3: SPI with UART3
 253 * PSC2: UART
 254 * PSC1: UART
 255 */
 256#define CONFIG_SYS_GPS_PORT_CONFIG      0x10559C44
 257
 258/*
 259 * Miscellaneous configurable options
 260 */
 261#define CONFIG_SYS_LONGHELP             1       /* undef to save memory */
 262#define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size */
 263#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 264#define CONFIG_SYS_MAXARGS              16      /* max number of command args */
 265#define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 266
 267#define CONFIG_SYS_ALT_MEMTEST          1
 268#define CONFIG_SYS_MEMTEST_START        0x00100000      /* memtest works on */
 269#define CONFIG_SYS_MEMTEST_END          0x03f00000      /* 1 .. 63 MiB in SDRAM */
 270
 271#define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 272
 273/*
 274 * Various low-level settings
 275 */
 276#define CONFIG_SYS_HID0_INIT            HID0_ICE | HID0_ICFI
 277#define CONFIG_SYS_HID0_FINAL           HID0_ICE
 278
 279#define CONFIG_SYS_XLB_PIPELINING       1       /* enable transaction pipeling */
 280
 281/*
 282 * Cache Configuration
 283 */
 284#define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC5xxx CPUs */
 285#ifdef CONFIG_CMD_KGDB
 286#define CONFIG_SYS_CACHELINE_SHIFT      5       /* log base 2 of the above value */
 287#endif
 288
 289/*
 290 * Flat Device Tree support
 291 */
 292#define OF_CPU                  "PowerPC,5200@0"
 293#define OF_SOC                  "soc5200@f0000000"
 294#define OF_TBCLK                (bd->bi_busfreq / 4)
 295#define OF_STDOUT_PATH          "/soc5200@f0000000/serial@2000"
 296
 297#endif /* __CONFIG_H */
 298