LXR uboot/include/configs/cm

   1/*
   2 * (C) Copyright 2011 CompuLab, Ltd.
   3 * Mike Rapoport <mike@compulab.co.il>
   4 * Igor Grinberg <grinberg@compulab.co.il>
   5 *
   6 * Based on omap3_beagle.h
   7 * (C) Copyright 2006-2008
   8 * Texas Instruments.
   9 * Richard Woodruff <r-woodruff2@ti.com>
  10 * Syed Mohammed Khasim <x0khasim@ti.com>
  11 *
  12 * Configuration settings for the CompuLab CM-T35 and CM-T3730 boards
  13 *
  14 * SPDX-License-Identifier:     GPL-2.0+
  15 */
  16
  17#ifndef __CONFIG_H
  18#define __CONFIG_H
  19
  20#define CONFIG_SYS_CACHELINE_SIZE       64
  21
  22/*
  23 * High Level Configuration Options
  24 */
  25#define CONFIG_OMAP     /* in a TI OMAP core */
  26#define CONFIG_OMAP_GPIO
  27#define CONFIG_CM_T3X   /* working with CM-T35 and CM-T3730 */
  28
  29#define CONFIG_SDRC     /* The chip has SDRC controller */
  30
  31#include <asm/arch/cpu.h>               /* get chip and board defs */
  32#include <asm/arch/omap.h>
  33
  34/* Clock Defines */
  35#define V_OSCK                  26000000        /* Clock output from T2 */
  36#define V_SCLK                  (V_OSCK >> 1)
  37
  38#define CONFIG_MISC_INIT_R
  39
  40#define CONFIG_CMDLINE_TAG              /* enable passing of ATAGs */
  41#define CONFIG_SETUP_MEMORY_TAGS
  42#define CONFIG_INITRD_TAG
  43#define CONFIG_REVISION_TAG
  44#define CONFIG_SERIAL_TAG
  45
  46/*
  47 * Size of malloc() pool
  48 */
  49#define CONFIG_ENV_SIZE         (16 << 10)      /* 16 KiB */
  50                                        /* Sector */
  51#define CONFIG_SYS_MALLOC_LEN   (CONFIG_ENV_SIZE + (128 << 10))
  52
  53/*
  54 * Hardware drivers
  55 */
  56
  57/*
  58 * NS16550 Configuration
  59 */
  60#define V_NS16550_CLK                   48000000        /* 48MHz (APLL96/2) */
  61
  62#define CONFIG_SYS_NS16550_SERIAL
  63#define CONFIG_SYS_NS16550_REG_SIZE     (-4)
  64#define CONFIG_SYS_NS16550_CLK          V_NS16550_CLK
  65
  66/*
  67 * select serial console configuration
  68 */
  69#define CONFIG_CONS_INDEX               3
  70#define CONFIG_SYS_NS16550_COM3         OMAP34XX_UART3
  71#define CONFIG_SERIAL3                  3       /* UART3 */
  72
  73/* allow to overwrite serial and ethaddr */
  74#define CONFIG_ENV_OVERWRITE
  75#define CONFIG_SYS_BAUDRATE_TABLE       {4800, 9600, 19200, 38400, 57600,\
  76                                        115200}
  77
  78/* USB */
  79#define CONFIG_USB_OMAP3
  80#define CONFIG_USB_EHCI
  81#define CONFIG_USB_EHCI_OMAP
  82#define CONFIG_USB_MUSB_UDC
  83#define CONFIG_TWL4030_USB
  84
  85/* USB device configuration */
  86#define CONFIG_USB_DEVICE
  87#define CONFIG_USB_TTY
  88
  89/* commands to include */
  90#define CONFIG_CMD_MTDPARTS     /* Enable MTD parts commands */
  91#define CONFIG_MTD_DEVICE       /* needed for mtdparts commands */
  92#define CONFIG_MTD_PARTITIONS
  93#define MTDIDS_DEFAULT          "nand0=nand"
  94#define MTDPARTS_DEFAULT        "mtdparts=nand:512k(x-loader),"\
  95                                "1920k(u-boot),256k(u-boot-env),"\
  96                                "4m(kernel),-(fs)"
  97
  98#define CONFIG_CMD_NAND         /* NAND support                 */
  99
 100#define CONFIG_SYS_I2C
 101#define CONFIG_SYS_OMAP24_I2C_SPEED     100000
 102#define CONFIG_SYS_OMAP24_I2C_SLAVE     1
 103#define CONFIG_SYS_I2C_OMAP34XX
 104#define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
 105#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 106#define CONFIG_SYS_I2C_EEPROM_BUS       0
 107#define CONFIG_I2C_MULTI_BUS
 108
 109/*
 110 * TWL4030
 111 */
 112#define CONFIG_TWL4030_POWER
 113#define CONFIG_TWL4030_LED
 114
 115/*
 116 * Board NAND Info.
 117 */
 118#define CONFIG_NAND_OMAP_GPMC
 119#define CONFIG_SYS_NAND_ADDR            NAND_BASE       /* physical address */
 120                                                        /* to access nand */
 121#define CONFIG_SYS_NAND_BASE            NAND_BASE       /* physical address */
 122                                                        /* to access nand at */
 123                                                        /* CS0 */
 124#define CONFIG_SYS_MAX_NAND_DEVICE      1               /* Max number of NAND */
 125                                                        /* devices */
 126
 127/* Environment information */
 128#define CONFIG_EXTRA_ENV_SETTINGS \
 129        "loadaddr=0x82000000\0" \
 130        "usbtty=cdc_acm\0" \
 131        "console=ttyO2,115200n8\0" \
 132        "mpurate=500\0" \
 133        "vram=12M\0" \
 134        "dvimode=1024x768MR-16@60\0" \
 135        "defaultdisplay=dvi\0" \
 136        "mmcdev=0\0" \
 137        "mmcroot=/dev/mmcblk0p2 rw\0" \
 138        "mmcrootfstype=ext4 rootwait\0" \
 139        "nandroot=/dev/mtdblock4 rw\0" \
 140        "nandrootfstype=ubifs\0" \
 141        "mmcargs=setenv bootargs console=${console} " \
 142                "mpurate=${mpurate} " \
 143                "vram=${vram} " \
 144                "omapfb.mode=dvi:${dvimode} " \
 145                "omapdss.def_disp=${defaultdisplay} " \
 146                "root=${mmcroot} " \
 147                "rootfstype=${mmcrootfstype}\0" \
 148        "nandargs=setenv bootargs console=${console} " \
 149                "mpurate=${mpurate} " \
 150                "vram=${vram} " \
 151                "omapfb.mode=dvi:${dvimode} " \
 152                "omapdss.def_disp=${defaultdisplay} " \
 153                "root=${nandroot} " \
 154                "rootfstype=${nandrootfstype}\0" \
 155        "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
 156        "bootscript=echo Running bootscript from mmc ...; " \
 157                "source ${loadaddr}\0" \
 158        "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
 159        "mmcboot=echo Booting from mmc ...; " \
 160                "run mmcargs; " \
 161                "bootm ${loadaddr}\0" \
 162        "nandboot=echo Booting from nand ...; " \
 163                "run nandargs; " \
 164                "nand read ${loadaddr} 2a0000 400000; " \
 165                "bootm ${loadaddr}\0" \
 166
 167#define CONFIG_BOOTCOMMAND \
 168        "mmc dev ${mmcdev}; if mmc rescan; then " \
 169                "if run loadbootscript; then " \
 170                        "run bootscript; " \
 171                "else " \
 172                        "if run loaduimage; then " \
 173                                "run mmcboot; " \
 174                        "else run nandboot; " \
 175                        "fi; " \
 176                "fi; " \
 177        "else run nandboot; fi"
 178
 179/*
 180 * Miscellaneous configurable options
 181 */
 182#define CONFIG_AUTO_COMPLETE
 183#define CONFIG_CMDLINE_EDITING
 184#define CONFIG_TIMESTAMP
 185#define CONFIG_SYS_AUTOLOAD             "no"
 186#define CONFIG_SYS_LONGHELP             /* undef to save memory */
 187#define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size */
 188/* Print Buffer Size */
 189#define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
 190                                        sizeof(CONFIG_SYS_PROMPT) + 16)
 191#define CONFIG_SYS_MAXARGS              16      /* max number of command args */
 192/* Boot Argument Buffer Size */
 193#define CONFIG_SYS_BARGSIZE             (CONFIG_SYS_CBSIZE)
 194
 195#define CONFIG_SYS_MEMTEST_START        (OMAP34XX_SDRC_CS0)     /* memtest */
 196                                                                /* works on */
 197#define CONFIG_SYS_MEMTEST_END          (OMAP34XX_SDRC_CS0 + \
 198                                        0x01F00000) /* 31MB */
 199
 200#define CONFIG_SYS_LOAD_ADDR            (OMAP34XX_SDRC_CS0)     /* default */
 201                                                        /* load address */
 202
 203/*
 204 * OMAP3 has 12 GP timers, they can be driven by the system clock
 205 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 206 * This rate is divided by a local divisor.
 207 */
 208#define CONFIG_SYS_TIMERBASE            (OMAP34XX_GPT2)
 209#define CONFIG_SYS_PTV                  2       /* Divisor: 2^(PTV+1) => 8 */
 210
 211/*-----------------------------------------------------------------------
 212 * Physical Memory Map
 213 */
 214#define CONFIG_NR_DRAM_BANKS    1       /* CS1 is never populated */
 215#define PHYS_SDRAM_1            OMAP34XX_SDRC_CS0
 216
 217/*-----------------------------------------------------------------------
 218 * FLASH and environment organization
 219 */
 220
 221/* **** PISMO SUPPORT *** */
 222/* Monitor at start of flash */
 223#define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_FLASH_BASE
 224#define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 2 sectors */
 225
 226#define CONFIG_ENV_IS_IN_NAND
 227#define SMNAND_ENV_OFFSET               0x260000 /* environment starts here */
 228#define CONFIG_ENV_OFFSET               SMNAND_ENV_OFFSET
 229#define CONFIG_ENV_ADDR                 SMNAND_ENV_OFFSET
 230
 231#if defined(CONFIG_CMD_NET)
 232#define CONFIG_SMC911X
 233#define CONFIG_SMC911X_32_BIT
 234#define CM_T3X_SMC911X_BASE     0x2C000000
 235#define SB_T35_SMC911X_BASE     (CM_T3X_SMC911X_BASE + (16 << 20))
 236#define CONFIG_SMC911X_BASE     CM_T3X_SMC911X_BASE
 237#endif /* (CONFIG_CMD_NET) */
 238
 239/* additions for new relocation code, must be added to all boards */
 240#define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
 241#define CONFIG_SYS_INIT_RAM_ADDR        0x4020f800
 242#define CONFIG_SYS_INIT_RAM_SIZE        0x800
 243#define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_INIT_RAM_ADDR +     \
 244                                         CONFIG_SYS_INIT_RAM_SIZE -     \
 245                                         GENERATED_GBL_DATA_SIZE)
 246
 247/* Status LED */
 248#define GREEN_LED_GPIO                  186 /* CM-T35 Green LED is GPIO186 */
 249
 250#define CONFIG_SPLASHIMAGE_GUARD
 251
 252/* GPIO banks */
 253#ifdef CONFIG_LED_STATUS
 254#define CONFIG_OMAP3_GPIO_6     /* GPIO186 is in GPIO bank 6  */
 255#endif
 256
 257/* Display Configuration */
 258#define CONFIG_OMAP3_GPIO_2
 259#define CONFIG_OMAP3_GPIO_5
 260#define CONFIG_VIDEO_OMAP3
 261#define LCD_BPP         LCD_COLOR16
 262
 263#define CONFIG_SPLASH_SCREEN
 264#define CONFIG_SPLASH_SOURCE
 265#define CONFIG_BMP_16BPP
 266#define CONFIG_SCF0403_LCD
 267
 268#define CONFIG_OMAP3_SPI
 269
 270/* Defines for SPL */
 271#define CONFIG_SPL_FRAMEWORK
 272#define CONFIG_SPL_NAND_SIMPLE
 273
 274#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION      1
 275#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
 276
 277#define CONFIG_SPL_BOARD_INIT
 278#define CONFIG_SPL_NAND_BASE
 279#define CONFIG_SPL_NAND_DRIVERS
 280#define CONFIG_SPL_NAND_ECC
 281#define CONFIG_SPL_OMAP3_ID_NAND
 282#define CONFIG_SPL_LDSCRIPT             "arch/arm/mach-omap2/u-boot-spl.lds"
 283
 284/* NAND boot config */
 285#define CONFIG_SYS_NAND_5_ADDR_CYCLE
 286#define CONFIG_SYS_NAND_PAGE_COUNT      64
 287#define CONFIG_SYS_NAND_PAGE_SIZE       2048
 288#define CONFIG_SYS_NAND_OOBSIZE         64
 289#define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 290#define CONFIG_SYS_NAND_BAD_BLOCK_POS   NAND_LARGE_BADBLOCK_POS
 291/*
 292 * Use the ECC/OOB layout from omap_gpmc.h that matches your chip:
 293 * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT
 294 */
 295#define CONFIG_SYS_NAND_ECCPOS          { 1, 2, 3, 4, 5, 6, 7, 8, 9, \
 296                                         10, 11, 12 }
 297#define CONFIG_SYS_NAND_ECCSIZE         512
 298#define CONFIG_SYS_NAND_ECCBYTES        3
 299#define CONFIG_NAND_OMAP_ECCSCHEME      OMAP_ECC_HAM1_CODE_HW
 300
 301#define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
 302#define CONFIG_SYS_NAND_U_BOOT_OFFS     0x80000
 303
 304#define CONFIG_SPL_TEXT_BASE            0x40200800
 305#define CONFIG_SPL_MAX_SIZE             (SRAM_SCRATCH_SPACE_ADDR - \
 306                                         CONFIG_SPL_TEXT_BASE)
 307
 308/*
 309 * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the
 310 * older x-loader implementations. And move the BSS area so that it
 311 * doesn't overlap with TEXT_BASE.
 312 */
 313#define CONFIG_SYS_TEXT_BASE            0x80008000
 314#define CONFIG_SPL_BSS_START_ADDR       0x80100000
 315#define CONFIG_SPL_BSS_MAX_SIZE         0x80000         /* 512 KB */
 316
 317#define CONFIG_SYS_SPL_MALLOC_START     0x80208000
 318#define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
 319
 320/* EEPROM */
 321#define CONFIG_CMD_EEPROM
 322#define CONFIG_ENV_EEPROM_IS_ON_I2C
 323#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 324#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       4
 325#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   5
 326#define CONFIG_SYS_EEPROM_SIZE                  256
 327
 328#define CONFIG_CMD_EEPROM_LAYOUT
 329#define CONFIG_EEPROM_LAYOUT_HELP_STRING "legacy, v1, v2, v3"
 330
 331#endif /* __CONFIG_H */
 332