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25
26#ifndef __CONFIG_H
27#define __CONFIG_H
28
29#ifdef CONFIG_SDCARD
30#define CONFIG_RAMBOOT_SDCARD
31#endif
32
33#ifdef CONFIG_SPIFLASH
34#define CONFIG_RAMBOOT_SPIFLASH
35#endif
36
37
38#define CONFIG_CONTROLCENTERD
39#define CONFIG_MP
40
41#define CONFIG_ENABLE_36BIT_PHYS
42
43#ifdef CONFIG_PHYS_64BIT
44#define CONFIG_ADDR_MAP
45#define CONFIG_SYS_NUM_ADDR_MAP 16
46#endif
47
48#define CONFIG_L2_CACHE
49#define CONFIG_BTB
50
51#define CONFIG_SYS_CLK_FREQ 66666600
52#define CONFIG_DDR_CLK_FREQ 66666600
53
54#define CONFIG_SYS_RAMBOOT
55
56#ifdef CONFIG_TRAILBLAZER
57
58#define CONFIG_SYS_TEXT_BASE 0xf8fc0000
59#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
60#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
61
62
63
64
65#define CONFIG_SYS_INIT_L2_ADDR 0xf8fc0000
66#ifdef CONFIG_PHYS_64BIT
67#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8fc0000ull
68#else
69#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
70#endif
71#define CONFIG_SYS_L2_SIZE (256 << 10)
72#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
73
74#else
75
76#define CONFIG_SYS_TEXT_BASE 0x11000000
77#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
78#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
79
80#endif
81
82#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
83#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
84
85
86
87
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89
90
91
92
93
94
95
96
97
98
99#define CONFIG_SYS_INIT_RAM_LOCK
100#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000
101#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
102#define CONFIG_SYS_GBL_DATA_OFFSET \
103 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
104#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
105
106#ifdef CONFIG_TRAILBLAZER
107
108#define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT
109#else
110#define CONFIG_SYS_CCSRBAR 0xffe00000
111#endif
112#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
113#define CONFIG_SYS_MPC85xx_GPIO3_ADDR (CONFIG_SYS_CCSRBAR+0xf200)
114
115
116
117
118
119#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
120#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
121#define CONFIG_SYS_SDRAM_SIZE 1024
122#define CONFIG_VERY_BIG_RAM
123
124#define CONFIG_DIMM_SLOTS_PER_CTLR 1
125#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
126
127#define CONFIG_SYS_MEMTEST_START 0x00000000
128#define CONFIG_SYS_MEMTEST_END 0x3fffffff
129
130#ifdef CONFIG_TRAILBLAZER
131#define CONFIG_SPD_EEPROM
132#define SPD_EEPROM_ADDRESS 0x52
133
134#endif
135
136
137
138
139
140#define CONFIG_SYS_ELBC_BASE 0xe0000000
141#ifdef CONFIG_PHYS_64BIT
142#define CONFIG_SYS_ELBC_BASE_PHYS 0xfe0000000ull
143#else
144#define CONFIG_SYS_ELBC_BASE_PHYS CONFIG_SYS_ELBC_BASE
145#endif
146
147#define CONFIG_UART_BR_PRELIM \
148 (BR_PHYS_ADDR((CONFIG_SYS_ELBC_BASE_PHYS)) | BR_PS_8 | BR_V)
149#define CONFIG_UART_OR_PRELIM (OR_AM_32KB | 0xff7)
150
151#define CONFIG_SYS_BR0_PRELIM 0
152#define CONFIG_SYS_OR0_PRELIM 0
153
154#define CONFIG_SYS_BR1_PRELIM CONFIG_UART_BR_PRELIM
155#define CONFIG_SYS_OR1_PRELIM CONFIG_UART_OR_PRELIM
156
157
158
159
160#define CONFIG_CONS_INDEX 2
161#define CONFIG_SYS_NS16550_SERIAL
162#define CONFIG_SYS_NS16550_REG_SIZE 1
163#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
164
165#define CONFIG_SYS_BAUDRATE_TABLE \
166 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
167
168#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
169#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
170
171
172
173
174#define CONFIG_SYS_I2C
175#define CONFIG_SYS_I2C_FSL
176#define CONFIG_SYS_FSL_I2C_SPEED 400000
177#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
178#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
179#define CONFIG_SYS_FSL_I2C2_SPEED 400000
180#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
181#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
182
183#ifndef CONFIG_TRAILBLAZER
184#endif
185
186#define CONFIG_PCA9698
187
188#define CONFIG_CMD_EEPROM
189#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
190#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
191
192#ifndef CONFIG_TRAILBLAZER
193
194
195
196#define CONFIG_HARD_SPI
197
198#define CONFIG_SF_DEFAULT_SPEED 10000000
199#define CONFIG_SF_DEFAULT_MODE 0
200#endif
201
202#define CONFIG_SHA1
203
204
205
206
207#define CONFIG_FSL_ESDHC
208#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
209
210#ifndef CONFIG_TRAILBLAZER
211
212
213
214
215#define CONFIG_FSL_DIU_FB
216#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000)
217
218
219
220
221
222#define CONFIG_PCIE1
223#define CONFIG_PCI_INDIRECT_BRIDGE
224#define CONFIG_PCI_SCAN_SHOW
225#define CONFIG_SYS_PCI_64BIT
226#define CONFIG_CMD_PCI
227
228#define CONFIG_FSL_PCI_INIT
229#define CONFIG_FSL_PCIE_RESET
230
231#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
232#ifdef CONFIG_PHYS_64BIT
233#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
234#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
235#else
236#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
237#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
238#endif
239#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000
240#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
241#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
242#ifdef CONFIG_PHYS_64BIT
243#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
244#else
245#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
246#endif
247#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000
248
249
250
251
252#define CONFIG_LIBATA
253#define CONFIG_LBA48
254#define CONFIG_CMD_SATA
255
256#define CONFIG_FSL_SATA
257#define CONFIG_SYS_SATA_MAX_DEVICE 2
258#define CONFIG_SATA1
259#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
260#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
261#define CONFIG_SATA2
262#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
263#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
264
265
266
267
268#define CONFIG_TSEC_ENET
269
270#define CONFIG_TSECV2
271
272#define CONFIG_MII
273#define CONFIG_TSEC1 1
274#define CONFIG_TSEC1_NAME "eTSEC1"
275#define CONFIG_TSEC2 1
276#define CONFIG_TSEC2_NAME "eTSEC2"
277
278#define TSEC1_PHY_ADDR 0
279#define TSEC2_PHY_ADDR 1
280
281#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
282#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
283
284#define TSEC1_PHYIDX 0
285#define TSEC2_PHYIDX 0
286
287#define CONFIG_ETHPRIME "eTSEC1"
288
289#define CONFIG_PHY_GIGE
290
291
292
293
294#define CONFIG_USB_EHCI
295
296#define CONFIG_HAS_FSL_DR_USB
297#define CONFIG_USB_EHCI_FSL
298#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
299
300#endif
301
302
303
304
305#if defined(CONFIG_TRAILBLAZER)
306#define CONFIG_ENV_IS_NOWHERE
307#define CONFIG_ENV_SIZE 0x2000
308#elif defined(CONFIG_RAMBOOT_SPIFLASH)
309#define CONFIG_ENV_IS_IN_SPI_FLASH
310#define CONFIG_ENV_SPI_BUS 0
311#define CONFIG_ENV_SPI_CS 0
312#define CONFIG_ENV_SPI_MAX_HZ 10000000
313#define CONFIG_ENV_SPI_MODE 0
314#define CONFIG_ENV_SIZE 0x2000
315#define CONFIG_ENV_OFFSET 0x100000
316#define CONFIG_ENV_SECT_SIZE 0x10000
317#elif defined(CONFIG_RAMBOOT_SDCARD)
318#define CONFIG_ENV_IS_IN_MMC
319#define CONFIG_FSL_FIXED_MMC_LOCATION
320#define CONFIG_ENV_SIZE 0x2000
321#define CONFIG_SYS_MMC_ENV_DEV 0
322#endif
323
324#define CONFIG_SYS_EXTRA_ENV_RELOC
325
326
327
328
329#ifndef CONFIG_TRAILBLAZER
330#define CONFIG_SYS_LONGHELP
331#define CONFIG_CMDLINE_EDITING
332#define CONFIG_AUTO_COMPLETE
333#endif
334
335#define CONFIG_SYS_LOAD_ADDR 0x2000000
336#ifdef CONFIG_CMD_KGDB
337#define CONFIG_SYS_CBSIZE 1024
338#else
339#define CONFIG_SYS_CBSIZE 256
340#endif
341
342#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
343#define CONFIG_SYS_MAXARGS 16
344#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
345
346#ifndef CONFIG_TRAILBLAZER
347
348#define CONFIG_CMD_ERRATA
349#define CONFIG_CMD_IRQ
350#define CONFIG_CMD_REGINFO
351
352
353
354
355#define CONFIG_BOARD_EARLY_INIT_R
356#define CONFIG_MISC_INIT_R
357#define CONFIG_LAST_STAGE_INIT
358
359#else
360
361#define CONFIG_BOARD_EARLY_INIT_R
362#define CONFIG_LAST_STAGE_INIT
363
364#endif
365
366
367
368
369#define CONFIG_HW_WATCHDOG
370#define CONFIG_LOADS_ECHO
371#define CONFIG_SYS_LOADS_BAUD_CHANGE
372
373
374
375
376
377
378#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
379#define CONFIG_SYS_BOOTM_LEN (64 << 20)
380
381
382
383
384
385#ifdef CONFIG_TRAILBLAZER
386#define CONFIG_EXTRA_ENV_SETTINGS \
387 "mp_holdoff=1\0"
388
389#else
390
391#define CONFIG_HOSTNAME controlcenterd
392#define CONFIG_ROOTPATH "/opt/nfsroot"
393#define CONFIG_BOOTFILE "uImage"
394#define CONFIG_UBOOTPATH u-boot.bin
395
396#define CONFIG_LOADADDR 1000000
397
398#define CONFIG_EXTRA_ENV_SETTINGS \
399 "netdev=eth0\0" \
400 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
401 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
402 "tftpflash=tftpboot $loadaddr $uboot && " \
403 "protect off $ubootaddr +$filesize && " \
404 "erase $ubootaddr +$filesize && " \
405 "cp.b $loadaddr $ubootaddr $filesize && " \
406 "protect on $ubootaddr +$filesize && " \
407 "cmp.b $loadaddr $ubootaddr $filesize\0" \
408 "consoledev=ttyS1\0" \
409 "ramdiskaddr=2000000\0" \
410 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
411 "fdtaddr=1e00000\0" \
412 "fdtfile=controlcenterd.dtb\0" \
413 "bdev=sda3\0"
414
415
416#define CONFIG_NFSBOOTCOMMAND \
417 "setenv bootargs root=/dev/nfs rw " \
418 "nfsroot=$serverip:$rootpath " \
419 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
420 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
421 "tftp $loadaddr $bootfile;" \
422 "tftp $fdtaddr $fdtfile;" \
423 "bootm $loadaddr - $fdtaddr"
424
425#define CONFIG_RAMBOOTCOMMAND \
426 "setenv bootargs root=/dev/ram rw " \
427 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
428 "tftp $ramdiskaddr $ramdiskfile;" \
429 "tftp $loadaddr $bootfile;" \
430 "tftp $fdtaddr $fdtfile;" \
431 "bootm $loadaddr $ramdiskaddr $fdtaddr"
432
433#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
434
435#endif
436
437#endif
438