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11#ifndef __CONFIG_H
12#define __CONFIG_H
13
14
15
16
17#define CONFIG_DRIVER_TI_EMAC
18
19#ifndef CONFIG_DIRECT_NOR_BOOT
20#define CONFIG_USE_SPIFLASH
21#endif
22
23
24
25
26#define CONFIG_MACH_DAVINCI_DA850_EVM
27#define CONFIG_SOC_DA8XX
28#define CONFIG_SOC_DA850
29#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
30#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
31#define CONFIG_SYS_OSCIN_FREQ 24000000
32#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
33#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
34
35#ifdef CONFIG_DIRECT_NOR_BOOT
36#define CONFIG_ARCH_CPU_INIT
37#define CONFIG_DA8XX_GPIO
38#define CONFIG_SYS_TEXT_BASE 0x60000000
39#define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11)
40#define CONFIG_DA850_LOWLEVEL
41#else
42#define CONFIG_SYS_TEXT_BASE 0xc1080000
43#endif
44
45
46
47
48#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024)
49#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE
50#define PHYS_SDRAM_1_SIZE (64 << 20)
51#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20)
52
53
54#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
55
56
57#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
58
59#define CONFIG_NR_DRAM_BANKS 1
60
61#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \
62 DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
63 DAVINCI_SYSCFG_SUSPSRC_SPI1 | \
64 DAVINCI_SYSCFG_SUSPSRC_UART2 | \
65 DAVINCI_SYSCFG_SUSPSRC_EMAC | \
66 DAVINCI_SYSCFG_SUSPSRC_I2C)
67
68
69
70
71#define CONFIG_SYS_DV_CLKMODE 0
72#define CONFIG_SYS_DA850_PLL0_POSTDIV 1
73#define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000
74#define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001
75#define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002
76#define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003
77#define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002
78#define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1
79#define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005
80
81#define CONFIG_SYS_DA850_PLL1_POSTDIV 1
82#define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000
83#define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001
84#define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8002
85
86#define CONFIG_SYS_DA850_PLL0_PLLM 24
87#define CONFIG_SYS_DA850_PLL1_PLLM 21
88
89
90
91
92#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
93 DV_DDR_PHY_EXT_STRBEN | \
94 (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
95
96#define CONFIG_SYS_DA850_DDR2_SDBCR ( \
97 (1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) | \
98 (1 << DV_DDR_SDCR_DDREN_SHIFT) | \
99 (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \
100 (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \
101 (0x3 << DV_DDR_SDCR_CL_SHIFT) | \
102 (0x2 << DV_DDR_SDCR_IBANK_SHIFT) | \
103 (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
104
105
106#define CONFIG_SYS_DA850_DDR2_SDBCR2 0
107
108#define CONFIG_SYS_DA850_DDR2_SDTIMR ( \
109 (14 << DV_DDR_SDTMR1_RFC_SHIFT) | \
110 (2 << DV_DDR_SDTMR1_RP_SHIFT) | \
111 (2 << DV_DDR_SDTMR1_RCD_SHIFT) | \
112 (1 << DV_DDR_SDTMR1_WR_SHIFT) | \
113 (5 << DV_DDR_SDTMR1_RAS_SHIFT) | \
114 (8 << DV_DDR_SDTMR1_RC_SHIFT) | \
115 (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \
116 (0 << DV_DDR_SDTMR1_WTR_SHIFT))
117
118#define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \
119 (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \
120 (0 << DV_DDR_SDTMR2_XP_SHIFT) | \
121 (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \
122 (17 << DV_DDR_SDTMR2_XSNR_SHIFT) | \
123 (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \
124 (0 << DV_DDR_SDTMR2_RTP_SHIFT) | \
125 (0 << DV_DDR_SDTMR2_CKE_SHIFT))
126
127#define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000494
128#define CONFIG_SYS_DA850_DDR2_PBBPR 0x30
129
130
131
132
133#define CONFIG_SYS_NS16550_SERIAL
134#define CONFIG_SYS_NS16550_REG_SIZE -4
135#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE
136#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
137#define CONFIG_CONS_INDEX 1
138
139#define CONFIG_SPI
140#define CONFIG_DAVINCI_SPI
141#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
142#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
143#define CONFIG_SF_DEFAULT_SPEED 30000000
144#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
145
146#ifdef CONFIG_USE_SPIFLASH
147#define CONFIG_SPL_SPI_LOAD
148#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000
149#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000
150#endif
151
152
153
154
155#define CONFIG_SYS_I2C
156#define CONFIG_SYS_I2C_DAVINCI
157#define CONFIG_SYS_DAVINCI_I2C_SPEED 25000
158#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10
159#define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20
160
161
162
163
164#ifdef CONFIG_USE_NAND
165#undef CONFIG_ENV_IS_IN_FLASH
166#define CONFIG_NAND_DAVINCI
167#define CONFIG_ENV_IS_IN_NAND
168#define CONFIG_ENV_OFFSET 0x0
169#define CONFIG_ENV_SIZE (128 << 10)
170#define CONFIG_SYS_NAND_USE_FLASH_BBT
171#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
172#define CONFIG_SYS_NAND_PAGE_2K
173#define CONFIG_SYS_NAND_CS 3
174#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
175#define CONFIG_SYS_NAND_MASK_CLE 0x10
176#define CONFIG_SYS_NAND_MASK_ALE 0x8
177#undef CONFIG_SYS_NAND_HW_ECC
178#define CONFIG_SYS_MAX_NAND_DEVICE 1
179#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
180#define CONFIG_SYS_NAND_5_ADDR_CYCLE
181#define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10)
182#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
183#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x28000
184#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x60000
185#define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000
186#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
187#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \
188 CONFIG_SYS_NAND_U_BOOT_SIZE - \
189 CONFIG_SYS_MALLOC_LEN - \
190 GENERATED_GBL_DATA_SIZE)
191#define CONFIG_SYS_NAND_ECCPOS { \
192 24, 25, 26, 27, 28, \
193 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \
194 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
195 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \
196 59, 60, 61, 62, 63 }
197#define CONFIG_SYS_NAND_PAGE_COUNT 64
198#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
199#define CONFIG_SYS_NAND_ECCSIZE 512
200#define CONFIG_SYS_NAND_ECCBYTES 10
201#define CONFIG_SYS_NAND_OOBSIZE 64
202#define CONFIG_SPL_NAND_BASE
203#define CONFIG_SPL_NAND_DRIVERS
204#define CONFIG_SPL_NAND_ECC
205#define CONFIG_SPL_NAND_SIMPLE
206#define CONFIG_SPL_NAND_LOAD
207#endif
208
209
210
211
212#ifdef CONFIG_DRIVER_TI_EMAC
213#define CONFIG_MII
214#define CONFIG_BOOTP_DNS
215#define CONFIG_BOOTP_DNS2
216#define CONFIG_BOOTP_SEND_HOSTNAME
217#define CONFIG_NET_RETRY_COUNT 10
218#endif
219
220#ifdef CONFIG_USE_NOR
221#define CONFIG_ENV_IS_IN_FLASH
222#define CONFIG_FLASH_CFI_DRIVER
223#define CONFIG_SYS_FLASH_CFI
224#define CONFIG_SYS_FLASH_PROTECTION
225#define CONFIG_SYS_MAX_FLASH_BANKS 1
226#define CONFIG_SYS_FLASH_SECT_SZ (128 << 10)
227#define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ * 3)
228#define CONFIG_ENV_SIZE (10 << 10)
229#define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
230#define PHYS_FLASH_SIZE (8 << 20)
231#define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\
232 + 3)
233#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ
234#endif
235
236#ifdef CONFIG_USE_SPIFLASH
237#undef CONFIG_ENV_IS_IN_FLASH
238#undef CONFIG_ENV_IS_IN_NAND
239#define CONFIG_ENV_IS_IN_SPI_FLASH
240#define CONFIG_ENV_SIZE (64 << 10)
241#define CONFIG_ENV_OFFSET (512 << 10)
242#define CONFIG_ENV_SECT_SIZE (64 << 10)
243#endif
244
245
246
247
248#define CONFIG_MISC_INIT_R
249#define CONFIG_BOOTFILE "uImage"
250#define CONFIG_SYS_CBSIZE 1024
251#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
252#define CONFIG_SYS_MAXARGS 16
253#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
254#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
255#define CONFIG_AUTO_COMPLETE
256#define CONFIG_CMDLINE_EDITING
257#define CONFIG_SYS_LONGHELP
258#define CONFIG_CRC32_VERIFY
259#define CONFIG_MX_CYCLIC
260
261
262
263
264#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
265#define CONFIG_HWCONFIG
266#define CONFIG_CMDLINE_TAG
267#define CONFIG_REVISION_TAG
268#define CONFIG_SETUP_MEMORY_TAGS
269#define CONFIG_BOOTARGS \
270 "mem=32M console=ttyS2,115200n8 root=/dev/mtdblock2 rw noinitrd ip=dhcp"
271#define CONFIG_EXTRA_ENV_SETTINGS "hwconfig=dsp:wake=yes"
272
273
274
275
276#define CONFIG_CMD_ENV
277#define CONFIG_CMD_SAVES
278
279#ifdef CONFIG_CMD_BDI
280#define CONFIG_CLOCKS
281#endif
282
283#ifndef CONFIG_DRIVER_TI_EMAC
284#endif
285
286#ifdef CONFIG_USE_NAND
287#define CONFIG_CMD_NAND
288
289#define CONFIG_CMD_MTDPARTS
290#define CONFIG_MTD_DEVICE
291#define CONFIG_MTD_PARTITIONS
292#define CONFIG_LZO
293#define CONFIG_RBTREE
294#define CONFIG_CMD_UBIFS
295#endif
296
297#ifdef CONFIG_USE_SPIFLASH
298#endif
299
300#if !defined(CONFIG_USE_NAND) && \
301 !defined(CONFIG_USE_NOR) && \
302 !defined(CONFIG_USE_SPIFLASH)
303#define CONFIG_ENV_IS_NOWHERE
304#define CONFIG_ENV_SIZE (16 << 10)
305#undef CONFIG_CMD_ENV
306#endif
307
308#ifndef CONFIG_DIRECT_NOR_BOOT
309
310#define CONFIG_SPL_FRAMEWORK
311#define CONFIG_SPL_BOARD_INIT
312#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \
313 CONFIG_SYS_MALLOC_LEN)
314#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
315#define CONFIG_SPL_SPI_LOAD
316#define CONFIG_SPL_LDSCRIPT "board/$(BOARDDIR)/u-boot-spl-da850evm.lds"
317#define CONFIG_SPL_STACK 0x8001ff00
318#define CONFIG_SPL_TEXT_BASE 0x80000000
319#define CONFIG_SPL_MAX_FOOTPRINT 32768
320#define CONFIG_SPL_PAD_TO 32768
321#endif
322
323
324#ifdef CONFIG_SPL_MMC_LOAD
325#undef CONFIG_SPL_SPI_LOAD
326#endif
327
328
329#define CONFIG_SYS_SDRAM_BASE 0xc0000000
330
331#ifdef CONFIG_DIRECT_NOR_BOOT
332#define CONFIG_SYS_INIT_SP_ADDR 0x8001ff00
333#else
334#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
335 GENERATED_GBL_DATA_SIZE)
336#endif
337#endif
338