LXR uboot/include/configs/digsy

   1/*
   2 * (C) Copyright 2003-2004
   3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4 *
   5 * (C) Copyright 2005-2007
   6 * Modified for InterControl digsyMTC MPC5200 board by
   7 * Frank Bodammer, GCD Hard- & Software GmbH,
   8 *                 frank.bodammer@gcd-solutions.de
   9 *
  10 * (C) Copyright 2009 Semihalf
  11 * Optimized for digsyMTC by: Grzegorz Bernacki <gjb@semihalf.com>
  12 *
  13 * SPDX-License-Identifier:     GPL-2.0+
  14 */
  15
  16#ifndef __CONFIG_H
  17#define __CONFIG_H
  18
  19/*
  20 * High Level Configuration Options
  21 */
  22
  23#define CONFIG_MPC5200          1       /* This is an MPC5200 CPU */
  24#define CONFIG_DIGSY_MTC        1       /* ... on InterControl digsyMTC board */
  25
  26/*
  27 * Valid values for CONFIG_SYS_TEXT_BASE are:
  28 * 0xFFF00000   boot high (standard configuration)
  29 * 0xFE000000   boot low
  30 * 0x00100000   boot from RAM (for testing only)
  31 */
  32#ifndef CONFIG_SYS_TEXT_BASE
  33#define CONFIG_SYS_TEXT_BASE    0xFFF00000      /* Standard: boot high */
  34#endif
  35
  36#define CONFIG_SYS_MPC5XXX_CLKIN        33000000
  37
  38#define CONFIG_SYS_CACHELINE_SIZE       32
  39
  40/*
  41 * Serial console configuration
  42 */
  43#define CONFIG_PSC_CONSOLE      4       /* console is on PSC4  */
  44#define CONFIG_SYS_BAUDRATE_TABLE       \
  45        { 9600, 19200, 38400, 57600, 115200, 230400 }
  46
  47/*
  48 * PCI Mapping:
  49 * 0x40000000 - 0x4fffffff - PCI Memory
  50 * 0x50000000 - 0x50ffffff - PCI IO Space
  51 */
  52#define CONFIG_PCI_SCAN_SHOW    1
  53#define CONFIG_PCI_BOOTDELAY    250
  54
  55#define CONFIG_PCI_MEM_BUS      0x40000000
  56#define CONFIG_PCI_MEM_PHYS     CONFIG_PCI_MEM_BUS
  57#define CONFIG_PCI_MEM_SIZE     0x10000000
  58
  59#define CONFIG_PCI_IO_BUS       0x50000000
  60#define CONFIG_PCI_IO_PHYS      CONFIG_PCI_IO_BUS
  61#define CONFIG_PCI_IO_SIZE      0x01000000
  62
  63#define CONFIG_BZIP2
  64
  65/*
  66 * Video
  67 */
  68
  69#ifdef CONFIG_VIDEO
  70#define CONFIG_VIDEO_MB862xx
  71#define CONFIG_VIDEO_MB862xx_ACCEL
  72#define CONFIG_VIDEO_CORALP
  73#define CONFIG_VIDEO_LOGO
  74#define CONFIG_VIDEO_BMP_LOGO
  75#define CONFIG_SPLASH_SCREEN
  76#define CONFIG_VIDEO_BMP_GZIP
  77#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE  (2 << 20)       /* decompressed img */
  78
  79/* Coral-PA clock frequency, geo and other both 133MHz */
  80#define CONFIG_SYS_MB862xx_CCF  0x00050000
  81/* Video SDRAM parameters */
  82#define CONFIG_SYS_MB862xx_MMR  0x11d7fa72
  83#endif
  84
  85/*
  86 * Command line configuration.
  87 */
  88#define CONFIG_CMD_EEPROM
  89#define CONFIG_CMD_IDE
  90#define CONFIG_CMD_IRQ
  91#define CONFIG_CMD_PCI
  92#define CONFIG_CMD_REGINFO
  93#define CONFIG_CMD_SAVES
  94
  95#if (CONFIG_SYS_TEXT_BASE == 0xFF000000)
  96#define CONFIG_SYS_LOWBOOT      1
  97#endif
  98
  99/*
 100 * Autobooting
 101 */
 102
 103#undef  CONFIG_BOOTARGS
 104
 105#define CONFIG_EXTRA_ENV_SETTINGS                                       \
 106        "fw_image=digsyMPC.img\0"                                       \
 107        "mtcb_start=mtc led diag orange; run mtcb_1\0"                  \
 108        "mtcb_clearled=for x in user1 user2 usbpwr usbbusy; "           \
 109                "do mtc led $x; done\0"                                 \
 110        "mtcb_1=if mtc key; then run mtcb_clearled mtcb_update; "       \
 111                "else run mtcb_fw; fi\0"                                \
 112        "mtcb_fw=if bootm ff000000; then echo FIRMWARE OK!; "           \
 113                "else echo BAD FIRMWARE CRC!; mtc led diag red; fi\0"   \
 114        "mtcb_update=mtc led user1 orange;"                             \
 115                "while mtc key; do ; done; run mtcb_2;\0"               \
 116        "mtcb_2=mtc led user1 green 2; usb reset; run mtcb_usb1;\0"     \
 117        "mtcb_usb1=if fatload usb 0 400000 script.img; "                \
 118                "then run mtcb_doscript; else run mtcb_usb2; fi\0"      \
 119        "mtcb_usb2=if fatload usb 0 400000 $fw_image; "                 \
 120                "then run mtcb_dousb; else run mtcb_ide; fi\0"          \
 121        "mtcb_doscript=run mtcb_usbleds; mtc led user2 orange 2; "      \
 122                "run mtcb_wait_flickr mtcb_ds_1;\0"                     \
 123        "mtcb_ds_1=if imi 400000; then mtc led usbbusy; "               \
 124                "source 400000; else run mtcb_error; fi\0"              \
 125        "mtcb_dousb=run mtcb_usbleds mtcb_wait_flickr mtcb_du_1;\0"     \
 126        "mtcb_du_1=if imi 400000; then run mtcb_du_2; "                 \
 127                "else run mtcb_error; fi\0"                             \
 128        "mtcb_du_2=run mtcb_clear mtcb_prog; mtc led usbbusy; "         \
 129                "run mtcb_checkfw\0"                                    \
 130        "mtcb_checkfw=if imi ff000000; then run mtcb_success; "         \
 131                "else run mtcb_error; fi\0"                             \
 132        "mtcb_waitkey=mtc key; until test $? -eq 0; do mtc key; done\0" \
 133        "mtcb_wait_flickr=run mtcb_waitkey mtcb_uledflckr\0"            \
 134        "mtcb_usbleds=mtc led usbpwr green; mtc led usbbusy orange 1;\0"\
 135        "mtcb_uledflckr=mtc led user1 orange 11\0"                      \
 136        "mtcb_error=mtc led user1 red\0"                                \
 137        "mtcb_clear=erase ff000000 ff0fffff\0"                          \
 138        "mtcb_prog=cp.b 400000 ff000000 ${filesize}\0"                  \
 139        "mtcb_success=mtc led user1 green\0"                            \
 140        "mtcb_ide=if fatload ide 0 400000 $fw_image;"                   \
 141                "then run mtcb_doide; else run mtcb_error; fi\0"        \
 142        "mtcb_doide=mtc led user2 green 1;"                             \
 143                "run mtcb_wait_flickr mtcb_di_1;\0"                     \
 144        "mtcb_di_1=if imi 400000; then run mtcb_di_2;"                  \
 145                "else run mtcb_error; fi\0"                             \
 146        "mtcb_di_2=run mtcb_clear; run mtcb_prog mtcb_checkfw\0"        \
 147        "ramdisk_num_sector=16\0"                                       \
 148        "flash_base=ff000000\0"                                         \
 149        "flashdisk_size=e00000\0"                                       \
 150        "env_sector=fff60000\0"                                         \
 151        "flashdisk_start=ff100000\0"                                    \
 152        "load_cmd=tftp 400000 digsyMPC.img\0"                           \
 153        "clear_cmd=erase ff000000 ff0fffff\0"                           \
 154        "flash_cmd=cp.b 400000 ff000000 ${filesize}\0"                  \
 155        "update_cmd=run load_cmd; "                                     \
 156        "iminfo 400000; "                                               \
 157        "run clear_cmd flash_cmd; "                                     \
 158        "iminfo ff000000\0"                                             \
 159        "spi_driver=yes\0"                                              \
 160        "spi_watchdog=no\0"                                             \
 161        "ftps_start=yes\0"                                              \
 162        "ftps_user1=admin\0"                                            \
 163        "ftps_pass1=admin\0"                                            \
 164        "ftps_base1=/\0"                                                \
 165        "ftps_home1=/\0"                                                \
 166        "plc_sio_srv=no\0"                                              \
 167        "plc_sio_baud=57600\0"                                          \
 168        "plc_sio_parity=no\0"                                           \
 169        "plc_sio_stop=1\0"                                              \
 170        "plc_sio_com=2\0"                                               \
 171        "plc_eth_srv=yes\0"                                             \
 172        "plc_eth_port=1200\0"                                           \
 173        "plc_root=/ide/\0"                                              \
 174        "diag_level=0\0"                                                \
 175        "webvisu=no\0"                                                  \
 176        "plc_can1_routing=no\0"                                         \
 177        "plc_can1_baudrate=250\0"                                       \
 178        "plc_can2_routing=no\0"                                         \
 179        "plc_can2_baudrate=250\0"                                       \
 180        "plc_can3_routing=no\0"                                         \
 181        "plc_can3_baudrate=250\0"                                       \
 182        "plc_can4_routing=no\0"                                         \
 183        "plc_can4_baudrate=250\0"                                       \
 184        "netdev=eth0\0"                                                 \
 185        "console=ttyPSC0\0"                                             \
 186        "kernel_addr_r=400000\0"                                        \
 187        "fdt_addr_r=600000\0"                                           \
 188        "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 189        "nfsroot=${serverip}:${rootpath}\0"                             \
 190        "addip=setenv bootargs ${bootargs} "                            \
 191        "ip=${ipaddr}:${serverip}:${gatewayip}:"                        \
 192        "${netmask}:${hostname}:${netdev}:off panic=1\0"                \
 193        "addcons=setenv bootargs ${bootargs} console=${console},${baudrate}\0"\
 194        "rootpath=/opt/eldk/ppc_6xx\0"                                  \
 195        "net_nfs=tftp ${kernel_addr_r} ${bootfile};"                    \
 196                "tftp ${fdt_addr_r} ${fdt_file};"                       \
 197                "run nfsargs addip addcons;"                            \
 198                "bootm ${kernel_addr_r} - ${fdt_addr_r}\0"              \
 199        "load=tftp 200000 ${u-boot}\0"                                  \
 200        "update=protect off FFF00000 +${filesize};"                     \
 201                "erase FFF00000 +${filesize};"                          \
 202                "cp.b 200000 FFF00000 ${filesize};"                     \
 203                "protect on FFF00000 +${filesize}\0"                    \
 204        ""
 205
 206#define CONFIG_BOOTCOMMAND      "run mtcb_start"
 207
 208/*
 209 * I2C configuration
 210 */
 211#define CONFIG_HARD_I2C         1
 212#define CONFIG_SYS_I2C_MODULE   1
 213#define CONFIG_SYS_I2C_SPEED    100000
 214#define CONFIG_SYS_I2C_SLAVE    0x7F
 215
 216/*
 217 * EEPROM configuration
 218 */
 219#define CONFIG_SYS_I2C_EEPROM_ADDR              0x50    /* 1010000x */
 220#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 221#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 222#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   70
 223
 224/*
 225 * RTC configuration
 226 */
 227#if defined(CONFIG_DIGSY_REV5)
 228#define CONFIG_SYS_I2C_RTC_ADDR 0x56
 229#define CONFIG_RTC_RV3029
 230/* Enable 5k Ohm trickle charge resistor */
 231#define CONFIG_SYS_RV3029_TCR   0x20
 232#else
 233#define CONFIG_RTC_DS1337
 234#define CONFIG_SYS_I2C_RTC_ADDR 0x68
 235#define CONFIG_SYS_DS1339_TCR_VAL       0xAB    /* diode + 4k resistor */
 236#endif
 237
 238/*
 239 * Flash configuration
 240 */
 241#define CONFIG_SYS_FLASH_CFI            1
 242#define CONFIG_FLASH_CFI_DRIVER 1
 243
 244#if defined(CONFIG_DIGSY_REV5)
 245#define CONFIG_SYS_FLASH_BASE           0xFE000000
 246#define CONFIG_SYS_FLASH_BASE_CS1       0xFC000000
 247#define CONFIG_SYS_MAX_FLASH_BANKS      2
 248#define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE, \
 249                                        CONFIG_SYS_FLASH_BASE_CS1}
 250#define CONFIG_SYS_UPDATE_FLASH_SIZE
 251#define CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
 252#else
 253#define CONFIG_SYS_FLASH_BASE           0xFF000000
 254#define CONFIG_SYS_MAX_FLASH_BANKS      1
 255#define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 256#endif
 257
 258#define CONFIG_SYS_MAX_FLASH_SECT       256
 259#define CONFIG_FLASH_16BIT
 260#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
 261#define CONFIG_SYS_FLASH_SIZE   0x01000000
 262#define CONFIG_SYS_FLASH_ERASE_TOUT     240000
 263#define CONFIG_SYS_FLASH_WRITE_TOUT     500
 264
 265#define OF_CPU                  "PowerPC,5200@0"
 266#define OF_SOC                  "soc5200@f0000000"
 267#define OF_TBCLK                (bd->bi_busfreq / 4)
 268
 269#define CONFIG_BOARD_EARLY_INIT_R
 270#define CONFIG_MISC_INIT_R
 271
 272/*
 273 * Environment settings
 274 */
 275#define CONFIG_ENV_IS_IN_FLASH  1
 276#if defined(CONFIG_LOWBOOT)
 277#define CONFIG_ENV_ADDR         0xFF060000
 278#else   /* CONFIG_LOWBOOT */
 279#define CONFIG_ENV_ADDR         0xFFF60000
 280#endif  /* CONFIG_LOWBOOT */
 281#define CONFIG_ENV_SIZE         0x10000
 282#define CONFIG_ENV_SECT_SIZE    0x20000
 283#define CONFIG_ENV_OVERWRITE    1
 284
 285/*
 286 * Memory map
 287 */
 288#define CONFIG_SYS_MBAR         0xF0000000
 289#define CONFIG_SYS_SDRAM_BASE           0x00000000
 290#if !defined(CONFIG_SYS_LOWBOOT)
 291#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
 292#else
 293#define CONFIG_SYS_DEFAULT_MBAR 0xF0000000
 294#endif
 295
 296/*
 297 *  Use SRAM until RAM will be available
 298 */
 299#define CONFIG_SYS_INIT_RAM_ADDR        MPC5XXX_SRAM
 300#define CONFIG_SYS_INIT_RAM_SIZE                MPC5XXX_SRAM_SIZE
 301
 302#define CONFIG_SYS_GBL_DATA_OFFSET      \
 303        (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 304#define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 305
 306#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 307#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 308#define CONFIG_SYS_RAMBOOT              1
 309#endif
 310
 311#define CONFIG_SYS_MONITOR_LEN  (256 << 10)
 312#define CONFIG_SYS_MALLOC_LEN   (4096 << 10)
 313#define CONFIG_SYS_BOOTMAPSZ    (8 << 20)
 314
 315/*
 316 * Ethernet configuration
 317 */
 318#define CONFIG_MPC5xxx_FEC      1
 319#define CONFIG_MPC5xxx_FEC_MII100
 320#if defined(CONFIG_DIGSY_REV5)
 321#define CONFIG_PHY_ADDR         0x01
 322#else
 323#define CONFIG_PHY_ADDR         0x00
 324#endif
 325#define CONFIG_PHY_RESET_DELAY  1000
 326
 327#define CONFIG_NETCONSOLE               /* include NetConsole support   */
 328
 329/*
 330 * GPIO configuration
 331 * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1)
 332 *  Bit 0   (mask 0x80000000) : 0x1
 333 * SPI on Tmr2/3/4/5 pins
 334 *  Bit 2:3 (mask 0x30000000) : 0x2
 335 * ATA cs0/1 on csb_4/5
 336 *  Bit 6:7 (mask 0x03000000) : 0x2
 337 * Ethernet 100Mbit with MD
 338 *  Bits 12:15 (mask 0x000f0000): 0x5
 339 * USB - Two UARTs
 340 *  Bits 18:19 (mask 0x00003000) : 0x2
 341 * PSC3 - USB2 on PSC3
 342 *  Bits 20:23 (mask 0x00000f00) : 0x1
 343 * PSC2 - CAN1&2 on PSC2 pins
 344 *  Bits 25:27 (mask 0x00000070) : 0x1
 345 * PSC1 - AC97 functionality
 346 *  Bits 29:31 (mask 0x00000007) : 0x2
 347 */
 348#define CONFIG_SYS_GPS_PORT_CONFIG      0xA2552112
 349
 350/*
 351 * Miscellaneous configurable options
 352 */
 353#define CONFIG_SYS_LONGHELP
 354#define CONFIG_AUTO_COMPLETE    1
 355#define CONFIG_CMDLINE_EDITING  1
 356
 357#define CONFIG_MX_CYCLIC        1
 358
 359#define CONFIG_SYS_CBSIZE               1024
 360#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 361#define CONFIG_SYS_MAXARGS              32
 362#define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 363
 364#define CONFIG_SYS_ALT_MEMTEST
 365#define CONFIG_SYS_MEMTEST_SCRATCH      0x00001000
 366#define CONFIG_SYS_MEMTEST_START        0x00010000
 367#define CONFIG_SYS_MEMTEST_END          0x019fffff
 368
 369#define CONFIG_SYS_LOAD_ADDR            0x00100000
 370
 371/*
 372 * Various low-level settings
 373 */
 374#define CONFIG_SYS_SDRAM_CS1            1
 375#define CONFIG_SYS_XLB_PIPELINING       1
 376
 377#define CONFIG_SYS_HID0_INIT            HID0_ICE | HID0_ICFI
 378#define CONFIG_SYS_HID0_FINAL           HID0_ICE
 379
 380#if defined(CONFIG_SYS_LOWBOOT)
 381#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
 382#define CONFIG_SYS_BOOTCS_SIZE          CONFIG_SYS_FLASH_SIZE
 383#define CONFIG_SYS_BOOTCS_CFG           0x0002DD00
 384#endif
 385
 386#define CONFIG_SYS_CS4_START            0x60000000
 387#define CONFIG_SYS_CS4_SIZE             0x1000
 388#define CONFIG_SYS_CS4_CFG              0x0008FC00
 389
 390#define CONFIG_SYS_CS0_START            CONFIG_SYS_FLASH_BASE
 391#define CONFIG_SYS_CS0_SIZE             CONFIG_SYS_FLASH_SIZE
 392#define CONFIG_SYS_CS0_CFG              0x0002DD00
 393
 394#if defined(CONFIG_DIGSY_REV5)
 395#define CONFIG_SYS_CS1_START            CONFIG_SYS_FLASH_BASE_CS1
 396#define CONFIG_SYS_CS1_SIZE             CONFIG_SYS_FLASH_SIZE
 397#define CONFIG_SYS_CS1_CFG              0x0002DD00
 398#endif
 399
 400#define CONFIG_SYS_CS_BURST             0x00000000
 401#define CONFIG_SYS_CS_DEADCYCLE 0x11111111
 402
 403#if !defined(CONFIG_SYS_LOWBOOT)
 404#define CONFIG_SYS_RESET_ADDRESS        0xfff00100
 405#else
 406#define CONFIG_SYS_RESET_ADDRESS        0xff000100
 407#endif
 408
 409/*
 410 * USB
 411 */
 412#define CONFIG_USB_OHCI_NEW
 413#define CONFIG_SYS_OHCI_BE_CONTROLLER
 414
 415#define CONFIG_USB_CLOCK        0x00013333
 416#define CONFIG_USB_CONFIG       0x00002000
 417
 418#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      15
 419#define CONFIG_SYS_USB_OHCI_REGS_BASE   MPC5XXX_USB
 420#define CONFIG_SYS_USB_OHCI_SLOT_NAME   "mpc5200"
 421#define CONFIG_SYS_USB_OHCI_CPU_INIT
 422
 423/*
 424 * IDE/ATA
 425 */
 426#define CONFIG_IDE_RESET
 427#define CONFIG_IDE_PREINIT
 428
 429#define CONFIG_SYS_ATA_CS_ON_I2C2
 430#define CONFIG_SYS_IDE_MAXBUS           1
 431#define CONFIG_SYS_IDE_MAXDEVICE        1
 432
 433#define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 434#define CONFIG_SYS_ATA_BASE_ADDR        MPC5XXX_ATA
 435#define CONFIG_SYS_ATA_DATA_OFFSET      (0x0060)
 436#define CONFIG_SYS_ATA_REG_OFFSET       (CONFIG_SYS_ATA_DATA_OFFSET)
 437#define CONFIG_SYS_ATA_ALT_OFFSET       (0x005C)
 438#define CONFIG_SYS_ATA_STRIDE           4
 439
 440#define CONFIG_ATAPI            1
 441#define CONFIG_LBA48            1
 442
 443#endif /* __CONFIG_H */
 444