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8#ifndef __CONFIG_H
9#define __CONFIG_H
10
11#define CONFIG_405EP 1
12#define CONFIG_DLVISION_10G 1
13
14#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
15
16
17
18
19#define CONFIG_HOSTNAME dlvsion-10g
20#include "amcc-common.h"
21
22#define CONFIG_BOARD_EARLY_INIT_R
23#define CONFIG_MISC_INIT_R
24#define CONFIG_LAST_STAGE_INIT
25
26#define CONFIG_SYS_CLK_FREQ 33333333
27
28
29
30
31#define PLLMR0_DEFAULT PLLMR0_266_133_66
32#define PLLMR1_DEFAULT PLLMR1_266_133_66
33
34
35#define CONFIG_FIT_DISABLE_SHA256
36
37#define CONFIG_ENV_IS_IN_FLASH
38
39
40
41
42#define CONFIG_EXTRA_ENV_SETTINGS \
43 CONFIG_AMCC_DEF_ENV \
44 CONFIG_AMCC_DEF_ENV_POWERPC \
45 CONFIG_AMCC_DEF_ENV_NOR_UPD \
46 "kernel_addr=fc000000\0" \
47 "fdt_addr=fc1e0000\0" \
48 "ramdisk_addr=fc200000\0" \
49 ""
50
51#define CONFIG_PHY_ADDR 4
52#define CONFIG_HAS_ETH0
53#define CONFIG_HAS_ETH1
54#define CONFIG_PHY1_ADDR 0xc
55#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
56
57
58
59
60#define CONFIG_CMD_DTT
61#undef CONFIG_CMD_EEPROM
62#undef CONFIG_CMD_IRQ
63
64
65
66
67#define CONFIG_SDRAM_BANK0 1
68
69
70#define CONFIG_SYS_SDRAM_CL 3
71#define CONFIG_SYS_SDRAM_tRP 20
72#define CONFIG_SYS_SDRAM_tRC 66
73#define CONFIG_SYS_SDRAM_tRCD 20
74#define CONFIG_SYS_SDRAM_tRFC 66
75
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81
82
83
84
85#define CONFIG_CONS_INDEX 1
86#undef CONFIG_SYS_EXT_SERIAL_CLOCK
87#undef CONFIG_SYS_405_UART_ERRATA_59
88#define CONFIG_SYS_BASE_BAUD 691200
89
90
91
92
93#define CONFIG_SYS_I2C_PPC4XX
94#define CONFIG_SYS_I2C_PPC4XX_CH0
95#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
96#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
97
98#define CONFIG_SYS_I2C_IHS
99#define CONFIG_SYS_I2C_IHS_DUAL
100#define CONFIG_SYS_I2C_IHS_CH0
101#define CONFIG_SYS_I2C_IHS_SPEED_0 50000
102#define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F
103#define CONFIG_SYS_I2C_IHS_SPEED_0_1 50000
104#define CONFIG_SYS_I2C_IHS_SLAVE_0_1 0x7F
105#define CONFIG_SYS_I2C_IHS_CH1
106#define CONFIG_SYS_I2C_IHS_SPEED_1 50000
107#define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F
108#define CONFIG_SYS_I2C_IHS_SPEED_1_1 50000
109#define CONFIG_SYS_I2C_IHS_SLAVE_1_1 0x7F
110
111#define CONFIG_SYS_SPD_BUS_NUM 4
112
113
114#define CONFIG_SYS_DTT_BUS_NUM 4
115#define CONFIG_DTT_LM63 1
116#define CONFIG_DTT_SENSORS { 0x4c, 0x4e, 0x18 }
117#define CONFIG_DTT_PWM_LOOKUPTABLE \
118 { { 46, 10 }, { 48, 14 }, { 50, 19 }, { 52, 23 },\
119 { 54, 27 }, { 56, 31 }, { 58, 36 }, { 60, 40 } }
120#define CONFIG_DTT_TACH_LIMIT 0xa10
121
122#define CONFIG_SYS_ICS8N3QV01_I2C {1, 3}
123#define CONFIG_SYS_SIL1178_I2C {0, 2}
124#define CONFIG_SYS_DP501_I2C {0, 2}
125
126
127
128#define CONFIG_SYS_FLASH_BASE 0xFC000000
129#define CONFIG_SYS_FPGA0_BASE 0x7f100000
130#define CONFIG_SYS_FPGA1_BASE 0x7f200000
131#define CONFIG_SYS_LATCH_BASE 0x7f300000
132
133#define CONFIG_SYS_FPGA_BASE(k) \
134 (k ? CONFIG_SYS_FPGA1_BASE : CONFIG_SYS_FPGA0_BASE)
135
136#define CONFIG_SYS_FPGA_DONE(k) \
137 (k ? 0x2000 : 0x1000)
138
139#define CONFIG_SYS_FPGA_COUNT 2
140
141#define CONFIG_SYS_FPGA_PTR { \
142 (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, \
143 (struct ihs_fpga *)CONFIG_SYS_FPGA1_BASE }
144
145#define CONFIG_SYS_FPGA_COMMON
146
147#define CONFIG_SYS_LATCH0_RESET 0xffff
148#define CONFIG_SYS_LATCH0_BOOT 0xffff
149#define CONFIG_SYS_LATCH1_RESET 0xffbf
150#define CONFIG_SYS_LATCH1_BOOT 0xffff
151
152#define CONFIG_SYS_FPGA_NO_RFL_HI
153
154
155
156
157#define CONFIG_SYS_FLASH_CFI
158#define CONFIG_FLASH_CFI_DRIVER
159
160#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
161
162#define CONFIG_SYS_MAX_FLASH_BANKS 1
163#define CONFIG_SYS_MAX_FLASH_SECT 512
164
165#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
166#define CONFIG_SYS_FLASH_WRITE_TOUT 500
167
168#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
169
170#define CONFIG_SYS_FLASH_EMPTY_INFO
171#define CONFIG_SYS_FLASH_QUIET_TEST 1
172
173#ifdef CONFIG_ENV_IS_IN_FLASH
174#define CONFIG_ENV_SECT_SIZE 0x20000
175#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
176#define CONFIG_ENV_SIZE 0x2000
177
178
179#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
180#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
181#endif
182
183
184
185
186#define CONFIG_SYS_4xx_GPIO_TABLE { \
187{ \
188 \
189{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
190{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
191{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
192{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, \
193{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
194{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, \
195{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, \
196{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, \
197{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
198{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
199{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
200{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
201{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
202{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, \
203{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
204{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
205{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
206{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
207{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
208{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
209{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, \
210{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
211{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
212{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, \
213{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
214{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
215{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
216{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
217{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
218{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
219{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
220{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, \
221} \
222}
223
224
225
226
227
228#define CONFIG_SYS_TEMP_STACK_OCM 1
229
230
231#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
232#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
233#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR
234#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE
235
236#define CONFIG_SYS_GBL_DATA_OFFSET \
237 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
238#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
239
240
241
242
243
244
245#define CONFIG_SYS_EBC_PB0AP (EBC_BXAP_BME_ENABLED | \
246 EBC_BXAP_FWT_ENCODE(8) | \
247 EBC_BXAP_BWT_ENCODE(7) | \
248 EBC_BXAP_BCE_DISABLE | \
249 EBC_BXAP_BCT_2TRANS | \
250 EBC_BXAP_CSN_ENCODE(0) | \
251 EBC_BXAP_OEN_ENCODE(2) | \
252 EBC_BXAP_WBN_ENCODE(2) | \
253 EBC_BXAP_WBF_ENCODE(2) | \
254 EBC_BXAP_TH_ENCODE(4) | \
255 EBC_BXAP_RE_DISABLED | \
256 EBC_BXAP_SOR_NONDELAYED | \
257 EBC_BXAP_BEM_WRITEONLY | \
258 EBC_BXAP_PEN_DISABLED)
259#define CONFIG_SYS_EBC_PB0CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \
260 EBC_BXCR_BS_64MB | \
261 EBC_BXCR_BU_RW | \
262 EBC_BXCR_BW_16BIT)
263
264
265#define CONFIG_SYS_EBC_PB1AP (EBC_BXAP_BME_DISABLED | \
266 EBC_BXAP_TWT_ENCODE(5) | \
267 EBC_BXAP_BCE_DISABLE | \
268 EBC_BXAP_BCT_2TRANS | \
269 EBC_BXAP_CSN_ENCODE(0) | \
270 EBC_BXAP_OEN_ENCODE(2) | \
271 EBC_BXAP_WBN_ENCODE(1) | \
272 EBC_BXAP_WBF_ENCODE(1) | \
273 EBC_BXAP_TH_ENCODE(0) | \
274 EBC_BXAP_RE_DISABLED | \
275 EBC_BXAP_SOR_NONDELAYED | \
276 EBC_BXAP_BEM_WRITEONLY | \
277 EBC_BXAP_PEN_DISABLED)
278#define CONFIG_SYS_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA0_BASE) | \
279 EBC_BXCR_BS_1MB | \
280 EBC_BXCR_BU_RW | \
281 EBC_BXCR_BW_16BIT)
282
283
284#define CONFIG_SYS_EBC_PB2AP (EBC_BXAP_BME_DISABLED | \
285 EBC_BXAP_TWT_ENCODE(6) | \
286 EBC_BXAP_BCE_DISABLE | \
287 EBC_BXAP_BCT_2TRANS | \
288 EBC_BXAP_CSN_ENCODE(0) | \
289 EBC_BXAP_OEN_ENCODE(2) | \
290 EBC_BXAP_WBN_ENCODE(1) | \
291 EBC_BXAP_WBF_ENCODE(1) | \
292 EBC_BXAP_TH_ENCODE(0) | \
293 EBC_BXAP_RE_DISABLED | \
294 EBC_BXAP_SOR_NONDELAYED | \
295 EBC_BXAP_BEM_WRITEONLY | \
296 EBC_BXAP_PEN_DISABLED)
297#define CONFIG_SYS_EBC_PB2CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA1_BASE) | \
298 EBC_BXCR_BS_1MB | \
299 EBC_BXCR_BU_RW | \
300 EBC_BXCR_BW_16BIT)
301
302
303#define CONFIG_SYS_EBC_PB3AP (EBC_BXAP_BME_ENABLED | \
304 EBC_BXAP_FWT_ENCODE(8) | \
305 EBC_BXAP_BWT_ENCODE(4) | \
306 EBC_BXAP_BCE_DISABLE | \
307 EBC_BXAP_BCT_2TRANS | \
308 EBC_BXAP_CSN_ENCODE(0) | \
309 EBC_BXAP_OEN_ENCODE(1) | \
310 EBC_BXAP_WBN_ENCODE(1) | \
311 EBC_BXAP_WBF_ENCODE(1) | \
312 EBC_BXAP_TH_ENCODE(2) | \
313 EBC_BXAP_RE_DISABLED | \
314 EBC_BXAP_SOR_NONDELAYED | \
315 EBC_BXAP_BEM_WRITEONLY | \
316 EBC_BXAP_PEN_DISABLED)
317#define CONFIG_SYS_EBC_PB3CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_LATCH_BASE) | \
318 EBC_BXCR_BS_1MB | \
319 EBC_BXCR_BU_RW | \
320 EBC_BXCR_BW_16BIT)
321
322
323
324
325#define CONFIG_SYS_MPC92469AC
326#define CONFIG_SYS_OSD_SCREENS CONFIG_SYS_FPGA_COUNT
327#define CONFIG_SYS_DP501_DIFFERENTIAL
328#define CONFIG_SYS_DP501_VCAPCTRL0 0x01
329
330#endif
331