LXR uboot/include/configs/dlvision.h

   1/*
   2 * (C) Copyright 2009
   3 * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
   4 *
   5 * SPDX-License-Identifier:     GPL-2.0+
   6 */
   7
   8#ifndef __CONFIG_H
   9#define __CONFIG_H
  10
  11#define CONFIG_405EP            1       /* this is a PPC405 CPU */
  12#define CONFIG_DLVISION         1       /*  on a Neo board */
  13
  14#define CONFIG_SYS_TEXT_BASE    0xFFFC0000
  15
  16/*
  17 * Include common defines/options for all AMCC eval boards
  18 */
  19#define CONFIG_HOSTNAME         dlvision
  20#include "amcc-common.h"
  21
  22#define CONFIG_MISC_INIT_R              /* call misc_init_r */
  23
  24#define CONFIG_SYS_CLK_FREQ     33333333 /* external frequency to pll   */
  25
  26/*
  27 * Configure PLL
  28 */
  29#define PLLMR0_DEFAULT PLLMR0_266_133_66_33
  30#define PLLMR1_DEFAULT PLLMR1_266_133_66_33
  31
  32/* new uImage format support */
  33#define CONFIG_FIT_DISABLE_SHA256
  34
  35#define CONFIG_ENV_IS_IN_FLASH  /* use FLASH for environment vars */
  36
  37/*
  38 * Default environment variables
  39 */
  40#define CONFIG_EXTRA_ENV_SETTINGS                                       \
  41        CONFIG_AMCC_DEF_ENV                                             \
  42        CONFIG_AMCC_DEF_ENV_POWERPC                                     \
  43        CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
  44        "kernel_addr=fc000000\0"                                        \
  45        "fdt_addr=fc1e0000\0"                                           \
  46        "ramdisk_addr=fc200000\0"                                       \
  47        ""
  48
  49#define CONFIG_PHY_ADDR         4       /* PHY address                  */
  50#define CONFIG_HAS_ETH0
  51#define CONFIG_HAS_ETH1
  52#define CONFIG_PHY1_ADDR        0xc     /* EMAC1 PHY address            */
  53#define CONFIG_PHY_CLK_FREQ    EMAC_STACR_CLK_66MHZ
  54
  55/*
  56 * Commands additional to the ones defined in amcc-common.h
  57 */
  58#define CONFIG_CMD_DTT
  59#undef CONFIG_CMD_EEPROM
  60#undef CONFIG_CMD_IRQ
  61
  62/*
  63 * SDRAM configuration (please see cpu/ppc/sdram.[ch])
  64 */
  65#define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0 */
  66
  67/* SDRAM timings used in datasheet */
  68#define CONFIG_SYS_SDRAM_CL             3       /* CAS latency */
  69#define CONFIG_SYS_SDRAM_tRP           20       /* PRECHARGE command period */
  70#define CONFIG_SYS_SDRAM_tRC           66       /* ACTIVE-to-ACTIVE period */
  71#define CONFIG_SYS_SDRAM_tRCD          20       /* ACTIVE-to-READ delay */
  72#define CONFIG_SYS_SDRAM_tRFC          66       /* Auto refresh period */
  73
  74/*
  75 * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
  76 * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
  77 * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD.
  78 * The Linux BASE_BAUD define should match this configuration.
  79 *    baseBaud = cpuClock/(uartDivisor*16)
  80 * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
  81 * set Linux BASE_BAUD to 403200.
  82 */
  83#define CONFIG_CONS_INDEX       1       /* Use UART0                    */
  84#undef  CONFIG_SYS_EXT_SERIAL_CLOCK           /* external serial clock */
  85#undef  CONFIG_SYS_405_UART_ERRATA_59         /* 405GP/CR Rev. D silicon */
  86#define CONFIG_SYS_BASE_BAUD            691200
  87
  88/*
  89 * I2C stuff
  90 */
  91#define CONFIG_SYS_I2C_PPC4XX_SPEED_0           100000
  92
  93/*
  94 * FLASH organization
  95 */
  96#define CONFIG_SYS_FLASH_CFI            /* The flash is CFI compatible  */
  97#define CONFIG_FLASH_CFI_DRIVER         /* Use common CFI driver        */
  98
  99#define CONFIG_SYS_FLASH_BASE           0xFC000000
 100#define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 101
 102#define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of memory banks */
 103#define CONFIG_SYS_MAX_FLASH_SECT       512     /* max num of sectors per chip*/
 104
 105#define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase/ms */
 106#define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write/ms */
 107
 108#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buff'd writes */
 109
 110#define CONFIG_SYS_FLASH_EMPTY_INFO     /* 'E' for empty sector on flinfo */
 111#define CONFIG_SYS_FLASH_QUIET_TEST     1       /* no warn upon unknown flash */
 112
 113#ifdef CONFIG_ENV_IS_IN_FLASH
 114#define CONFIG_ENV_SECT_SIZE    0x20000 /* size of one complete sector */
 115#define CONFIG_ENV_ADDR         ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
 116#define CONFIG_ENV_SIZE         0x2000  /* Total Size of Environment Sector */
 117
 118/* Address and size of Redundant Environment Sector     */
 119#define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
 120#define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 121#endif
 122
 123/*
 124 * PPC405 GPIO Configuration
 125 */
 126#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO     Alternate1      */ \
 127{ \
 128/* GPIO Core 0 */ \
 129{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO0   PerBLast */ \
 130{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO1   TS1E */ \
 131{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO2   TS2E */ \
 132{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO3   TS1O */ \
 133{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO4   TS2O */ \
 134{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1      }, /* GPIO5   TS3 */ \
 135{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO6   TS4 */ \
 136{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO7   TS5 */ \
 137{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO8   TS6 */ \
 138{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO9   TrcClk */ \
 139{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10  PerCS1 */ \
 140{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11  PerCS2 */ \
 141{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12  PerCS3 */ \
 142{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13  PerCS4 */ \
 143{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14  PerAddr03 */ \
 144{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15  PerAddr04 */ \
 145{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16  PerAddr05 */ \
 146{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17  IRQ0 */ \
 147{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18  IRQ1 */ \
 148{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19  IRQ2 */ \
 149{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO20  IRQ3 */ \
 150{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO21  IRQ4 */ \
 151{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO22  IRQ5 */ \
 152{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO23  IRQ6 */ \
 153{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24  UART0_DCD */ \
 154{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25  UART0_DSR */ \
 155{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26  UART0_RI */ \
 156{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27  UART0_DTR */ \
 157{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28  UART1_Rx */ \
 158{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29  UART1_Tx */ \
 159{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO30  RejectPkt0 */ \
 160{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO31  RejectPkt1 */ \
 161} \
 162}
 163
 164/*
 165 * Definitions for initial stack pointer and data area (in data cache)
 166 */
 167/* use on chip memory (OCM) for temperary stack until sdram is tested */
 168#define CONFIG_SYS_TEMP_STACK_OCM        1
 169
 170/* On Chip Memory location */
 171#define CONFIG_SYS_OCM_DATA_ADDR        0xF8000000
 172#define CONFIG_SYS_OCM_DATA_SIZE        0x1000
 173#define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
 174#define CONFIG_SYS_INIT_RAM_SIZE        CONFIG_SYS_OCM_DATA_SIZE /* Size of used area */
 175
 176#define CONFIG_SYS_GBL_DATA_OFFSET \
 177        (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 178#define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 179
 180/*
 181 * External Bus Controller (EBC) Setup
 182 */
 183
 184/* Memory Bank 0 (NOR-FLASH) initialization */
 185#define CONFIG_SYS_EBC_PB0AP            0x92015480
 186/* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit */
 187#define CONFIG_SYS_EBC_PB0CR            0xFC0DA000
 188
 189/* Memory Bank 1 (NVRAM) initializatio */
 190#define CONFIG_SYS_EBC_PB1AP            0x92015480
 191/* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit  */
 192#define CONFIG_SYS_EBC_PB1CR            0xFB858000
 193
 194/* Memory Bank 2 (UART) initialization */
 195#define CONFIG_UART_BASE                0x7f100000
 196#define CONFIG_SYS_EBC_PB2AP            0x92015480
 197/* BAS=0x7f1,BS=1MB,BU=R/W,BW=8bit */
 198#define CONFIG_SYS_EBC_PB2CR            0x7f118000
 199
 200/* Memory Bank 3 (Latches) initialization */
 201#define CONFIG_SYS_LATCH_BASE           0x7f200000
 202#define CONFIG_SYS_EBC_PB3AP            0x92015480
 203/* BAS=0x7f2,BS=1MB,BU=R/W,BW=16bit */
 204#define CONFIG_SYS_EBC_PB3CR            0x7f21a000
 205
 206#endif  /* __CONFIG_H */
 207