1/* 2 * (C) Copyright 2008 3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de 4 * 5 * Based on include/configs/yosemite.h 6 * (C) Copyright 2005-2007 7 * Stefan Roese, DENX Software Engineering, sr@denx.de. 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12/* 13 * gdppc440etx.h - configuration for G&D 440EP/GR ETX-Module 14 */ 15#ifndef __CONFIG_H 16#define __CONFIG_H 17 18/* 19 * High Level Configuration Options 20 */ 21#define CONFIG_440GR 1 /* Specific PPC440GR support */ 22#define CONFIG_HOSTNAME gdppc440etx 23#define CONFIG_440 1 /* ... PPC440 family */ 24#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */ 25 26#define CONFIG_SYS_TEXT_BASE 0xFFF80000 27 28/* 29 * Include common defines/options for all AMCC eval boards 30 */ 31#include "amcc-common.h" 32 33#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ 34 35/* 36 * Base addresses -- Note these are effective addresses where the 37 * actual resources get mapped (not physical addresses) 38 */ 39#define CONFIG_SYS_FLASH_BASE 0xfc000000 /* start of FLASH */ 40#define CONFIG_SYS_PCI_MEMBASE 0xa0000000 /* mapped pci memory */ 41#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000 42#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000 43#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000 44 45/*Don't change either of these*/ 46#define CONFIG_SYS_PCI_BASE 0xe0000000 /* internal PCI regs */ 47/*Don't change either of these*/ 48 49#define CONFIG_SYS_USB_DEVICE 0x50000000 50#define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000 51 52/* 53 * Initial RAM & stack pointer (placed in SDRAM) 54 */ 55#define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram*/ 56#define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */ 57#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10) 58#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ 59 - GENERATED_GBL_DATA_SIZE) 60#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 61 62/* 63 * Serial Port 64 */ 65#define CONFIG_CONS_INDEX 2 /* Use UART1 */ 66#define CONFIG_SYS_NS16550_SERIAL 67#define CONFIG_SYS_NS16550_REG_SIZE 1 68#define CONFIG_SYS_NS16550_CLK get_serial_clock() 69#define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */ 70 71/* 72 * Environment 73 * Define here the location of the environment variables (FLASH or EEPROM). 74 * Note: DENX encourages to use redundant environment in FLASH. 75 */ 76#define CONFIG_ENV_IS_IN_FLASH 1 /* FLASH for env. vars*/ 77 78/* 79 * FLASH related 80 */ 81#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible*/ 82#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ 83#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* AMD RESET for STM 29W320DB!*/ 84 85#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 86#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors/chip */ 87 88#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout/Flash Erase (in ms)*/ 89#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout/Flash Write (in ms)*/ 90 91#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1/* use buffered writes (20x faster)*/ 92 93#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ 94 95#ifdef CONFIG_ENV_IS_IN_FLASH 96#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector*/ 97#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE) 98#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Env. Sector */ 99 100/* Address and size of Redundant Environment Sector */ 101#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) 102#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 103#endif /* CONFIG_ENV_IS_IN_FLASH */ 104 105/* 106 * DDR SDRAM 107 */ 108#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup*/ 109#define CONFIG_SYS_KBYTES_SDRAM (128 * 1024) /* 128MB */ 110#define CONFIG_SYS_SDRAM_BANKS (2) 111 112#define CONFIG_SDRAM_BANK0 113#define CONFIG_SDRAM_BANK1 114 115#define CONFIG_SYS_SDRAM0_TR0 0x410a4012 116#define CONFIG_SYS_SDRAM0_WDDCTR 0x40000000 117#define CONFIG_SYS_SDRAM0_RTR 0x04080000 118#define CONFIG_SYS_SDRAM0_CFG0 0x80000000 119 120#undef CONFIG_SDRAM_ECC 121 122/* 123 * I2C 124 */ 125#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 126 127/* 128 * Default environment variables 129 */ 130#define CONFIG_EXTRA_ENV_SETTINGS \ 131 CONFIG_AMCC_DEF_ENV \ 132 CONFIG_AMCC_DEF_ENV_POWERPC \ 133 CONFIG_AMCC_DEF_ENV_NOR_UPD \ 134 "kernel_addr=fc000000\0" \ 135 "ramdisk_addr=fc180000\0" \ 136 "" 137 138#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ 139#define CONFIG_PHY_ADDR 1 140#define CONFIG_PHY1_ADDR 3 141 142#ifdef DEBUG 143#define CONFIG_PANIC_HANG 144#endif 145 146/* 147 * Commands additional to the ones defined in amcc-common.h 148 */ 149#define CONFIG_CMD_PCI 150#undef CONFIG_CMD_EEPROM 151 152/* 153 * PCI stuff 154 */ 155 156/* General PCI */ 157#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 158#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup*/ 159#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to \ 160 CONFIG_SYS_PCI_MEMBASE*/ 161 162/* Board-specific PCI */ 163#define CONFIG_SYS_PCI_TARGET_INIT 164#define CONFIG_SYS_PCI_MASTER_INIT 165 166#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ 167#define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* tbd */ 168 169/* 170 * External Bus Controller (EBC) Setup 171 */ 172#define CONFIG_SYS_FLASH CONFIG_SYS_FLASH_BASE 173 174/* Memory Bank 0 (NOR-FLASH) initialization */ 175#define CONFIG_SYS_EBC_PB0AP 0x03017200 176#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH | 0xda000) 177 178#endif /* __CONFIG_H */ 179