LXR uboot/include/configs/inka4x0.h

   1/*
   2 * (C) Copyright 2009
   3 * Detlev Zundel, DENX Software Engineering, dzu@denx.de.
   4 *
   5 * (C) Copyright 2003-2005
   6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   7 *
   8 * SPDX-License-Identifier:     GPL-2.0+
   9 */
  10
  11#ifndef __CONFIG_H
  12#define __CONFIG_H
  13
  14/*
  15 * High Level Configuration Options
  16 * (easy to change)
  17 */
  18
  19#define CONFIG_MPC5200          1       /* This is an MPC5200 CPU       */
  20#define CONFIG_INKA4X0          1       /* INKA4x0 board                */
  21
  22/*
  23 * Valid values for CONFIG_SYS_TEXT_BASE are:
  24 * 0xFFE00000   boot low
  25 * 0x00100000   boot from RAM (for testing only)
  26 */
  27#ifndef CONFIG_SYS_TEXT_BASE
  28#define CONFIG_SYS_TEXT_BASE    0xFFE00000      /* Standard: boot low */
  29#endif
  30#define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds"
  31
  32#define CONFIG_SYS_MPC5XXX_CLKIN        33000000 /* ... running at 33.000000MHz         */
  33
  34#define CONFIG_MISC_INIT_F      1       /* Use misc_init_f()                    */
  35
  36#define CONFIG_HIGH_BATS        1       /* High BATs supported                  */
  37
  38/*
  39 * Serial console configuration
  40 */
  41#define CONFIG_PSC_CONSOLE      1       /* console is on PSC1   */
  42#define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200, 230400 }
  43
  44/*
  45 * PCI Mapping:
  46 * 0x40000000 - 0x4fffffff - PCI Memory
  47 * 0x50000000 - 0x50ffffff - PCI IO Space
  48 */
  49#define CONFIG_PCI_SCAN_SHOW    1
  50#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
  51
  52#define CONFIG_PCI_MEM_BUS      0x40000000
  53#define CONFIG_PCI_MEM_PHYS     CONFIG_PCI_MEM_BUS
  54#define CONFIG_PCI_MEM_SIZE     0x10000000
  55
  56#define CONFIG_PCI_IO_BUS       0x50000000
  57#define CONFIG_PCI_IO_PHYS      CONFIG_PCI_IO_BUS
  58#define CONFIG_PCI_IO_SIZE      0x01000000
  59
  60#define CONFIG_SYS_XLB_PIPELINING       1
  61
  62/* Partitions */
  63
  64/*
  65 * BOOTP options
  66 */
  67#define CONFIG_BOOTP_BOOTFILESIZE
  68#define CONFIG_BOOTP_BOOTPATH
  69#define CONFIG_BOOTP_GATEWAY
  70#define CONFIG_BOOTP_HOSTNAME
  71
  72/*
  73 * Command line configuration.
  74 */
  75#define CONFIG_CMD_IDE
  76#define CONFIG_CMD_PCI
  77
  78#define CONFIG_TIMESTAMP        1       /* Print image info with timestamp */
  79
  80#if (CONFIG_SYS_TEXT_BASE == 0xFFE00000)                /* Boot low */
  81#   define CONFIG_SYS_LOWBOOT           1
  82#endif
  83
  84/*
  85 * Autobooting
  86 */
  87
  88#define CONFIG_PREBOOT  "echo;" \
  89        "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
  90        "echo"
  91
  92#undef  CONFIG_BOOTARGS
  93
  94#define CONFIG_IPADDR           192.168.100.2
  95#define CONFIG_SERVERIP         192.168.100.1
  96#define CONFIG_NETMASK          255.255.255.0
  97#define HOSTNAME                inka4x0
  98#define CONFIG_BOOTFILE         "/tftpboot/inka4x0/uImage"
  99#define CONFIG_ROOTPATH         "/opt/eldk/ppc_6xx"
 100
 101#define CONFIG_EXTRA_ENV_SETTINGS                                       \
 102        "netdev=eth0\0"                                                 \
 103        "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 104                "nfsroot=${serverip}:${rootpath}\0"                     \
 105        "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 106        "addip=setenv bootargs ${bootargs} "                            \
 107                "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 108                ":${hostname}:${netdev}:off panic=1\0"                  \
 109        "addcons=setenv bootargs ${bootargs} "                          \
 110                "console=ttyS0,${baudrate}\0"                           \
 111        "flash_nfs=run nfsargs addip addcons;"                          \
 112                "bootm ${kernel_addr}\0"                                \
 113        "net_nfs=tftp 200000 ${bootfile};"                              \
 114                "run nfsargs addip addcons;bootm\0"                     \
 115        "enable_disp=mw.l 100000 04000000 1;"                           \
 116                "cp.l 100000 f0000b20 1;"                               \
 117                "cp.l 100000 f0000b28 1\0"                              \
 118        "ideargs=setenv bootargs root=/dev/hda1 rw\0"                   \
 119        "ide_boot=ext2load ide 0:1 200000 uImage;"                      \
 120                "run ideargs addip addcons enable_disp;bootm\0"         \
 121        "brightness=255\0"                                              \
 122        ""
 123
 124#define CONFIG_BOOTCOMMAND      "run ide_boot"
 125
 126/*
 127 * IPB Bus clocking configuration.
 128 */
 129#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK         /* define for 133MHz speed */
 130
 131/*
 132 * Flash configuration
 133 */
 134#define CONFIG_SYS_FLASH_CFI            1       /* Flash is CFI conformant */
 135#define CONFIG_FLASH_CFI_DRIVER 1
 136#define CONFIG_SYS_FLASH_BASE           0xffe00000
 137#define CONFIG_SYS_FLASH_SIZE           0x00200000
 138#define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of memory banks */
 139#define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 140#define CONFIG_SYS_MAX_FLASH_SECT       128     /* max num of sects on one chip */
 141#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster) */
 142
 143/*
 144 * Environment settings
 145 */
 146#define CONFIG_ENV_IS_IN_FLASH  1
 147#define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + 0x4000)
 148#define CONFIG_ENV_SIZE         0x2000
 149#define CONFIG_ENV_SECT_SIZE    0x2000
 150#define CONFIG_ENV_OVERWRITE    1
 151#define CONFIG_SYS_USE_PPCENV                   /* Environment embedded in sect .ppcenv */
 152
 153/*
 154 * Memory map
 155 */
 156#define CONFIG_SYS_MBAR         0xF0000000
 157#define CONFIG_SYS_SDRAM_BASE           0x00000000
 158#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
 159
 160/*
 161 * SDRAM controller configuration
 162 */
 163#undef CONFIG_SDR_MT48LC16M16A2
 164#undef CONFIG_DDR_MT46V16M16
 165#undef CONFIG_DDR_MT46V32M16
 166#undef CONFIG_DDR_HYB25D512160BF
 167#define CONFIG_DDR_K4H511638C
 168
 169/* Use ON-Chip SRAM until RAM will be available */
 170#define CONFIG_SYS_INIT_RAM_ADDR        MPC5XXX_SRAM
 171
 172/* preserve space for the post_word at end of on-chip SRAM */
 173#define MPC5XXX_SRAM_POST_SIZE (MPC5XXX_SRAM_SIZE - 4)
 174
 175#ifdef CONFIG_POST
 176#define CONFIG_SYS_INIT_RAM_SIZE        MPC5XXX_SRAM_POST_SIZE
 177#else
 178#define CONFIG_SYS_INIT_RAM_SIZE        MPC5XXX_SRAM_SIZE
 179#endif
 180
 181#define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 182#define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 183
 184#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
 185#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 186#   define CONFIG_SYS_RAMBOOT           1
 187#endif
 188
 189#define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 190#define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 191#define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 192
 193/*
 194 * Ethernet configuration
 195 */
 196#define CONFIG_MPC5xxx_FEC      1
 197#define CONFIG_MPC5xxx_FEC_MII100
 198/*
 199 * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
 200 */
 201/* #define CONFIG_MPC5xxx_FEC_MII10 */
 202#define CONFIG_PHY_ADDR         0x00
 203#define CONFIG_MII
 204
 205/*
 206 * GPIO configuration
 207 *
 208 * use CS1 as gpio_wkup_6 output
 209 *      Bit 0 (mask: 0x80000000): 0
 210 * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
 211 *      00 -> No Alternatives, I2C1 is used for onboard EEPROM
 212 *      01 -> CAN1 on I2C1, CAN2 on Tmr0/1 do not use on TQM5200 with onboard
 213 *            EEPROM
 214 * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
 215 * use PSC2 as UART: Bits 24-27 (mask: 0x00000070): 0100
 216 * use PSC3 as UART: Bits 20-23 (mask: 0x00000700): 0100
 217 * use PSC6 as UART: Bits  9-11 (mask: 0x00700000): 0101
 218 */
 219#define CONFIG_SYS_GPS_PORT_CONFIG      0x01501444
 220
 221/*
 222 * RTC configuration
 223 */
 224#define CONFIG_RTC_RTC4543      1       /* use external RTC */
 225
 226/*
 227 * Software (bit-bang) three wire serial configuration
 228 *
 229 * Note that we need the ifdefs because otherwise compilation of
 230 * mkimage.c fails.
 231 */
 232#define CONFIG_SOFT_TWS         1
 233
 234#ifdef TWS_IMPLEMENTATION
 235#include <mpc5xxx.h>
 236#include <asm/io.h>
 237
 238#define TWS_CE          MPC5XXX_GPIO_WKUP_PSC1_4 /* GPIO_WKUP_0 */
 239#define TWS_WR          MPC5XXX_GPIO_WKUP_PSC2_4 /* GPIO_WKUP_1 */
 240#define TWS_DATA        MPC5XXX_GPIO_SINT_PSC3_4 /* GPIO_SINT_0 */
 241#define TWS_CLK         MPC5XXX_GPIO_SINT_PSC3_5 /* GPIO_SINT_1 */
 242
 243static inline void tws_ce(unsigned bit)
 244{
 245        struct mpc5xxx_wu_gpio *wu_gpio =
 246                (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
 247        if (bit)
 248                setbits_8(&wu_gpio->dvo, TWS_CE);
 249        else
 250                clrbits_8(&wu_gpio->dvo, TWS_CE);
 251}
 252
 253static inline void tws_wr(unsigned bit)
 254{
 255        struct mpc5xxx_wu_gpio *wu_gpio =
 256                (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
 257        if (bit)
 258                setbits_8(&wu_gpio->dvo, TWS_WR);
 259        else
 260                clrbits_8(&wu_gpio->dvo, TWS_WR);
 261}
 262
 263static inline void tws_clk(unsigned bit)
 264{
 265        struct mpc5xxx_gpio *gpio =
 266                (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
 267        if (bit)
 268                setbits_8(&gpio->sint_dvo, TWS_CLK);
 269        else
 270                clrbits_8(&gpio->sint_dvo, TWS_CLK);
 271}
 272
 273static inline void tws_data(unsigned bit)
 274{
 275        struct mpc5xxx_gpio *gpio =
 276                (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
 277        if (bit)
 278                setbits_8(&gpio->sint_dvo, TWS_DATA);
 279        else
 280                clrbits_8(&gpio->sint_dvo, TWS_DATA);
 281}
 282
 283static inline unsigned tws_data_read(void)
 284{
 285        struct mpc5xxx_gpio *gpio =
 286                        (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
 287        return !!(in_8(&gpio->sint_ival) & TWS_DATA);
 288}
 289
 290static inline void tws_data_config_output(unsigned output)
 291{
 292        struct mpc5xxx_gpio *gpio =
 293                (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
 294        if (output)
 295                setbits_8(&gpio->sint_ddr, TWS_DATA);
 296        else
 297                clrbits_8(&gpio->sint_ddr, TWS_DATA);
 298}
 299#endif /* TWS_IMPLEMENTATION */
 300
 301/*
 302 * Miscellaneous configurable options
 303 */
 304#define CONFIG_SYS_LONGHELP                     /* undef to save memory     */
 305#if defined(CONFIG_CMD_KGDB)
 306#define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size  */
 307#else
 308#define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size  */
 309#endif
 310#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 311#define CONFIG_SYS_MAXARGS              16      /* max number of command args   */
 312#define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 313
 314#define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC5xxx CPUs                     */
 315#if defined(CONFIG_CMD_KGDB)
 316#  define CONFIG_SYS_CACHELINE_SHIFT    5       /* log base 2 of the above value        */
 317#endif
 318
 319/* Enable an alternate, more extensive memory test */
 320#define CONFIG_SYS_ALT_MEMTEST
 321
 322#define CONFIG_SYS_MEMTEST_START        0x00100000      /* memtest works on */
 323#define CONFIG_SYS_MEMTEST_END          0x00f00000      /* 1 ... 15 MB in DRAM  */
 324
 325#define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 326
 327/*
 328 * Various low-level settings
 329 */
 330#define CONFIG_SYS_HID0_INIT            HID0_ICE | HID0_ICFI
 331#define CONFIG_SYS_HID0_FINAL           HID0_ICE
 332
 333#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
 334#define CONFIG_SYS_BOOTCS_SIZE          CONFIG_SYS_FLASH_SIZE
 335#define CONFIG_SYS_BOOTCS_CFG           0x00087800 /* for pci_clk  = 66 MHz */
 336#define CONFIG_SYS_CS0_START            CONFIG_SYS_FLASH_BASE
 337#define CONFIG_SYS_CS0_SIZE             CONFIG_SYS_FLASH_SIZE
 338
 339/* 32Mbit SRAM @0x30000000 */
 340#define CONFIG_SYS_CS1_START            0x30000000
 341#define CONFIG_SYS_CS1_SIZE             0x00400000
 342#define CONFIG_SYS_CS1_CFG              0x31800 /* for pci_clk = 33 MHz */
 343
 344/* 2 quad UART @0x80000000 (MBAR is relocated to 0xF0000000) */
 345#define CONFIG_SYS_CS2_START            0x80000000
 346#define CONFIG_SYS_CS2_SIZE             0x0001000
 347#define CONFIG_SYS_CS2_CFG              0x21800  /* for pci_clk = 33 MHz */
 348
 349/* GPIO in @0x30400000 */
 350#define CONFIG_SYS_CS3_START            0x30400000
 351#define CONFIG_SYS_CS3_SIZE             0x00100000
 352#define CONFIG_SYS_CS3_CFG              0x31800 /* for pci_clk = 33 MHz */
 353
 354#define CONFIG_SYS_CS_BURST             0x00000000
 355#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
 356
 357/*-----------------------------------------------------------------------
 358 * USB stuff
 359 *-----------------------------------------------------------------------
 360 */
 361#define CONFIG_USB_OHCI
 362#define CONFIG_USB_CLOCK        0x00015555
 363#define CONFIG_USB_CONFIG       0x00001000
 364
 365/*-----------------------------------------------------------------------
 366 * IDE/ATA stuff Supports IDE harddisk
 367 *-----------------------------------------------------------------------
 368 */
 369
 370#undef  CONFIG_IDE_8xx_PCCARD           /* Use IDE with PC Card Adapter */
 371
 372#undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 373#undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 374
 375#define CONFIG_IDE_PREINIT
 376
 377#define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus               */
 378#define CONFIG_SYS_IDE_MAXDEVICE        2       /* max. 1 drive per IDE bus     */
 379
 380#define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 381#define CONFIG_SYS_ATA_BASE_ADDR        MPC5XXX_ATA
 382#define CONFIG_SYS_ATA_DATA_OFFSET      0x0060  /* Offset for data I/O          */
 383#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) /* Offset for normal register accesses */
 384#define CONFIG_SYS_ATA_ALT_OFFSET       0x005C  /* Offset for alternate registers */
 385#define CONFIG_SYS_ATA_STRIDE          4        /* Interval between registers   */
 386
 387#define CONFIG_ATAPI            1
 388
 389#define CONFIG_SYS_BRIGHTNESS          0xFF     /* LCD Default Brightness (255 = off) */
 390
 391#endif /* __CONFIG_H */
 392