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8#ifndef __CONFIG_H
9#define __CONFIG_H
10
11#define CONFIG_405EP 1
12#define CONFIG_IO 1
13
14#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
15
16
17
18
19#define CONFIG_HOSTNAME io
20#include "amcc-common.h"
21
22#define CONFIG_BOARD_EARLY_INIT_R
23#define CONFIG_MISC_INIT_R
24#define CONFIG_LAST_STAGE_INIT
25
26#define CONFIG_SYS_CLK_FREQ 33333333
27
28
29
30
31#define PLLMR0_DEFAULT PLLMR0_266_133_66
32#define PLLMR1_DEFAULT PLLMR1_266_133_66
33
34
35#define CONFIG_FIT_DISABLE_SHA256
36
37#define CONFIG_ENV_IS_IN_FLASH
38
39
40
41
42#define CONFIG_EXTRA_ENV_SETTINGS \
43 CONFIG_AMCC_DEF_ENV \
44 CONFIG_AMCC_DEF_ENV_POWERPC \
45 CONFIG_AMCC_DEF_ENV_NOR_UPD \
46 "kernel_addr=fc000000\0" \
47 "fdt_addr=fc1e0000\0" \
48 "ramdisk_addr=fc200000\0" \
49 ""
50
51#define CONFIG_PHY_ADDR 4
52#define CONFIG_HAS_ETH0
53#define CONFIG_HAS_ETH1
54#define CONFIG_PHY1_ADDR 0xc
55#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
56
57
58
59
60#define CONFIG_CMD_DTT
61#undef CONFIG_CMD_EEPROM
62#undef CONFIG_CMD_IRQ
63
64
65
66
67#define CONFIG_SDRAM_BANK0 1
68
69
70#define CONFIG_SYS_SDRAM_CL 3
71#define CONFIG_SYS_SDRAM_tRP 20
72#define CONFIG_SYS_SDRAM_tRC 66
73#define CONFIG_SYS_SDRAM_tRCD 20
74#define CONFIG_SYS_SDRAM_tRFC 66
75
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82
83
84
85#define CONFIG_CONS_INDEX 1
86#undef CONFIG_SYS_EXT_SERIAL_CLOCK
87#undef CONFIG_SYS_405_UART_ERRATA_59
88#define CONFIG_SYS_BASE_BAUD 691200
89
90
91
92
93#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
94
95
96#define CONFIG_DTT_LM63 1
97#define CONFIG_DTT_SENSORS { 0 }
98#define CONFIG_DTT_PWM_LOOKUPTABLE \
99 { { 40, 10 }, { 50, 20 }, { 60, 40 } }
100#define CONFIG_DTT_TACH_LIMIT 0xa10
101
102
103
104
105#define CONFIG_SYS_FLASH_CFI
106#define CONFIG_FLASH_CFI_DRIVER
107
108#define CONFIG_SYS_FLASH_BASE 0xFC000000
109#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
110
111#define CONFIG_SYS_MAX_FLASH_BANKS 1
112#define CONFIG_SYS_MAX_FLASH_SECT 512
113
114#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
115#define CONFIG_SYS_FLASH_WRITE_TOUT 500
116
117#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
118
119#define CONFIG_SYS_FLASH_EMPTY_INFO
120#define CONFIG_SYS_FLASH_QUIET_TEST 1
121
122#ifdef CONFIG_ENV_IS_IN_FLASH
123#define CONFIG_ENV_SECT_SIZE 0x20000
124#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
125#define CONFIG_ENV_SIZE 0x2000
126
127
128#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
129#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
130#endif
131
132
133#define CONFIG_BITBANGMII
134#define CONFIG_BITBANGMII_MULTI
135
136#define CONFIG_SYS_MDIO_PIN (0x80000000 >> 13)
137#define CONFIG_SYS_MDC_PIN (0x80000000 >> 7)
138
139#define CONFIG_SYS_GBIT_MII_BUSNAME "io_miiphy"
140
141
142
143
144#define CONFIG_SYS_4xx_GPIO_TABLE { \
145{ \
146 \
147{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
148{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
149{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
150{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, \
151{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
152{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, \
153{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, \
154{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, \
155{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
156{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
157{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
158{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
159{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
160{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, \
161{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
162{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
163{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
164{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
165{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
166{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
167{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, \
168{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
169{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
170{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, \
171{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
172{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
173{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
174{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
175{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
176{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
177{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
178{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, \
179} \
180}
181
182
183
184
185
186#define CONFIG_SYS_TEMP_STACK_OCM 1
187
188
189#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
190#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
191#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR
192#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE
193
194#define CONFIG_SYS_GBL_DATA_OFFSET \
195 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
196#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
197
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201
202
203#define CONFIG_SYS_EBC_PB0AP 0xa382a880
204
205#define CONFIG_SYS_EBC_PB0CR 0xFC0DA000
206
207
208#define CONFIG_SYS_EBC_PB1AP 0x92015480
209
210#define CONFIG_SYS_EBC_PB1CR 0x7f318000
211
212
213#define CONFIG_SYS_FPGA0_BASE 0x7f100000
214#define CONFIG_SYS_EBC_PB2AP 0x02025080
215
216#define CONFIG_SYS_EBC_PB2CR 0x7f11a000
217
218#define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE
219#define CONFIG_SYS_FPGA_DONE(k) 0x0010
220
221#define CONFIG_SYS_FPGA_COUNT 1
222
223#define CONFIG_SYS_FPGA_PTR \
224 { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE }
225
226#define CONFIG_SYS_FPGA_COMMON
227
228
229#define CONFIG_SYS_LATCH_BASE 0x7f200000
230#define CONFIG_SYS_EBC_PB3AP 0xa2015480
231
232#define CONFIG_SYS_EBC_PB3CR 0x7f21a000
233
234#define CONFIG_SYS_LATCH0_RESET 0xffff
235#define CONFIG_SYS_LATCH0_BOOT 0xffff
236#define CONFIG_SYS_LATCH1_RESET 0xffbf
237#define CONFIG_SYS_LATCH1_BOOT 0xffff
238
239#endif
240