LXR uboot/include/configs/katmai.h

   1/*
   2 * (C) Copyright 2007
   3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4 *
   5 * (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com>
   6 *
   7 * SPDX-License-Identifier:     GPL-2.0+
   8 */
   9
  10/************************************************************************
  11 * katmai.h - configuration for AMCC Katmai (440SPe)
  12 ***********************************************************************/
  13
  14#ifndef __CONFIG_H
  15#define __CONFIG_H
  16
  17/*-----------------------------------------------------------------------
  18 * High Level Configuration Options
  19 *----------------------------------------------------------------------*/
  20#define CONFIG_KATMAI                   1       /* Board is Katmai      */
  21#define CONFIG_440                      1       /* ... PPC440 family    */
  22#define CONFIG_440SPE                   1       /* Specifc SPe support  */
  23#define CONFIG_440SPE_REVA              1       /* Support old Rev A.   */
  24#define CONFIG_SYS_CLK_FREQ     33333333        /* external freq to pll */
  25#define CONFIG_SYS_4xx_RESET_TYPE       0x2     /* use chip reset on this board */
  26
  27#define CONFIG_SYS_TEXT_BASE    0xFFFA0000
  28
  29/*
  30 * Enable this board for more than 2GB of SDRAM
  31 */
  32#define CONFIG_VERY_BIG_RAM
  33
  34/*
  35 * Include common defines/options for all AMCC eval boards
  36 */
  37#define CONFIG_HOSTNAME         katmai
  38#include "amcc-common.h"
  39
  40#undef  CONFIG_SHOW_BOOT_PROGRESS
  41
  42/*-----------------------------------------------------------------------
  43 * Base addresses -- Note these are effective addresses where the
  44 * actual resources get mapped (not physical addresses)
  45 *----------------------------------------------------------------------*/
  46#define CONFIG_SYS_FLASH_BASE           0xff000000      /* start of FLASH       */
  47#define CONFIG_SYS_ISRAM_BASE           0x90000000      /* internal SRAM        */
  48
  49#define CONFIG_SYS_PCI_MEMBASE          0x80000000      /* mapped PCI memory    */
  50#define CONFIG_SYS_PCI_BASE             0xd0000000      /* internal PCI regs    */
  51#define CONFIG_SYS_PCI_TARGBASE CONFIG_SYS_PCI_MEMBASE
  52
  53#define CONFIG_SYS_PCIE_MEMBASE 0xb0000000      /* mapped PCIe memory   */
  54#define CONFIG_SYS_PCIE_MEMSIZE 0x08000000      /* smallest incr for PCIe port */
  55#define CONFIG_SYS_PCIE_BASE            0xe0000000      /* PCIe UTL regs */
  56
  57#define CONFIG_SYS_PCIE0_CFGBASE        0xc0000000
  58#define CONFIG_SYS_PCIE1_CFGBASE        0xc1000000
  59#define CONFIG_SYS_PCIE2_CFGBASE        0xc2000000
  60#define CONFIG_SYS_PCIE0_XCFGBASE       0xc3000000
  61#define CONFIG_SYS_PCIE1_XCFGBASE       0xc3001000
  62#define CONFIG_SYS_PCIE2_XCFGBASE       0xc3002000
  63
  64/* base address of inbound PCIe window */
  65#define CONFIG_SYS_PCIE_INBOUND_BASE    0x0000000000000000ULL
  66
  67/* System RAM mapped to PCI space */
  68#define CONFIG_PCI_SYS_MEM_BUS  CONFIG_SYS_SDRAM_BASE
  69#define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE
  70#define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
  71
  72#define CONFIG_SYS_ACE_BASE             0xfe000000      /* Xilinx ACE controller - Compact Flash */
  73
  74/*-----------------------------------------------------------------------
  75 * Initial RAM & stack pointer (placed in internal SRAM)
  76 *----------------------------------------------------------------------*/
  77#define CONFIG_SYS_TEMP_STACK_OCM       1
  78#define CONFIG_SYS_OCM_DATA_ADDR        CONFIG_SYS_ISRAM_BASE
  79#define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_ISRAM_BASE   /* Initial RAM address  */
  80#define CONFIG_SYS_INIT_RAM_SIZE        0x2000          /* Size of used area in RAM */
  81
  82#define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  83#define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
  84
  85/*-----------------------------------------------------------------------
  86 * Serial Port
  87 *----------------------------------------------------------------------*/
  88#define CONFIG_CONS_INDEX       1       /* Use UART0                    */
  89#undef CONFIG_SYS_EXT_SERIAL_CLOCK
  90
  91/*-----------------------------------------------------------------------
  92 * DDR SDRAM
  93 *----------------------------------------------------------------------*/
  94#define CONFIG_SPD_EEPROM       1       /* Use SPD EEPROM for setup     */
  95#define SPD_EEPROM_ADDRESS      {0x51, 0x52}    /* SPD i2c spd addresses*/
  96#define CONFIG_DDR_ECC          1       /* with ECC support             */
  97#define CONFIG_DDR_RQDC_FIXED   0x80000038 /* optimal value found by GDA*/
  98#undef  CONFIG_STRESS
  99
 100/*-----------------------------------------------------------------------
 101 * I2C
 102 *----------------------------------------------------------------------*/
 103#define CONFIG_SYS_I2C_PPC4XX_SPEED_0           100000
 104
 105#define CONFIG_SYS_SPD_BUS_NUM          0       /* The I2C bus for SPD          */
 106
 107#define IIC0_BOOTPROM_ADDR      0x50
 108#define IIC0_ALT_BOOTPROM_ADDR  0x54
 109
 110#define CONFIG_SYS_I2C_EEPROM_ADDR      (0x50)
 111#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 112#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 113#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
 114
 115/* I2C bootstrap EEPROM */
 116#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR       0x50
 117#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET     0
 118#define CONFIG_4xx_CONFIG_BLOCKSIZE             8
 119
 120/* I2C RTC */
 121#define CONFIG_RTC_M41T11       1
 122#define CONFIG_SYS_RTC_BUS_NUM          1       /* The I2C bus for RTC          */
 123#define CONFIG_SYS_I2C_RTC_ADDR 0x68
 124#define CONFIG_SYS_M41T11_BASE_YEAR     1900    /* play along with linux        */
 125
 126/* I2C DTT */
 127#define CONFIG_DTT_ADM1021      1       /* ADM1021 temp sensor support  */
 128#define CONFIG_SYS_DTT_BUS_NUM          1       /* The I2C bus for DTT          */
 129/*
 130 * standard dtt sensor configuration - bottom bit will determine local or
 131 * remote sensor of the ADM1021, the rest determines index into
 132 * CONFIG_SYS_DTT_ADM1021 array below.
 133 */
 134#define CONFIG_DTT_SENSORS      { 0, 1 }
 135
 136/*
 137 * ADM1021 temp sensor configuration (see dtt/adm1021.c for details).
 138 * there will be one entry in this array for each two (dummy) sensors in
 139 * CONFIG_DTT_SENSORS.
 140 *
 141 * For Katmai board:
 142 * - only one ADM1021
 143 * - i2c addr 0x18
 144 * - conversion rate 0x02 = 0.25 conversions/second
 145 * - ALERT ouput disabled
 146 * - local temp sensor enabled, min set to 0 deg, max set to 85 deg
 147 * - remote temp sensor enabled, min set to 0 deg, max set to 85 deg
 148 */
 149#define CONFIG_SYS_DTT_ADM1021          { { 0x18, 0x02, 0, 1, 0, 85, 1, 0, 58} }
 150
 151/*-----------------------------------------------------------------------
 152 * Environment
 153 *----------------------------------------------------------------------*/
 154#define CONFIG_ENV_IS_IN_FLASH  1       /* Environment uses flash       */
 155
 156/*
 157 * Default environment variables
 158 */
 159#define CONFIG_EXTRA_ENV_SETTINGS                                       \
 160        CONFIG_AMCC_DEF_ENV                                             \
 161        CONFIG_AMCC_DEF_ENV_POWERPC                                     \
 162        CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
 163        "kernel_addr=ff000000\0"                                        \
 164        "fdt_addr=ff1e0000\0"                                           \
 165        "ramdisk_addr=ff200000\0"                                       \
 166        "pciconfighost=1\0"                                             \
 167        "pcie_mode=RP:RP:RP\0"                                          \
 168        ""
 169
 170/*
 171 * Commands additional to the ones defined in amcc-common.h
 172 */
 173#define CONFIG_CMD_ECCTEST
 174#define CONFIG_CMD_PCI
 175#define CONFIG_CMD_SDRAM
 176
 177#define CONFIG_IBM_EMAC4_V4     1       /* 440SPe has this EMAC version */
 178#define CONFIG_PHY_ADDR         1       /* PHY address, See schematics  */
 179#define CONFIG_HAS_ETH0
 180#define CONFIG_PHY_RESET        1       /* reset phy upon startup       */
 181#define CONFIG_PHY_RESET_DELAY  1000
 182#define CONFIG_CIS8201_PHY      1       /* Enable 'special' RGMII mode for Cicada phy */
 183#define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 184
 185/*-----------------------------------------------------------------------
 186 * FLASH related
 187 *----------------------------------------------------------------------*/
 188#define CONFIG_SYS_FLASH_CFI
 189#define CONFIG_FLASH_CFI_DRIVER
 190#define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
 191#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster)     */
 192
 193#define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE}
 194#define CONFIG_SYS_MAX_FLASH_BANKS     1                    /* number of banks      */
 195#define CONFIG_SYS_MAX_FLASH_SECT       1024                /* sectors per device   */
 196
 197#undef  CONFIG_SYS_FLASH_CHECKSUM
 198#define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 199#define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 200
 201#define CONFIG_ENV_SECT_SIZE    0x20000 /* size of one complete sector  */
 202#define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
 203#define CONFIG_ENV_SIZE         0x4000  /* Total Size of Environment Sector     */
 204
 205/* Address and size of Redundant Environment Sector     */
 206#define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
 207#define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 208
 209/*-----------------------------------------------------------------------
 210 * PCI stuff
 211 *-----------------------------------------------------------------------
 212 */
 213/* General PCI */
 214#define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 215#define CONFIG_PCI_SCAN_SHOW    1       /* show pci devices on startup  */
 216#define CONFIG_PCI_CONFIG_HOST_BRIDGE
 217
 218/* Board-specific PCI */
 219#define CONFIG_SYS_PCI_TARGET_INIT              /* let board init pci target    */
 220#undef  CONFIG_SYS_PCI_MASTER_INIT
 221
 222#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014   /* IBM                          */
 223#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe   /* Whatever                     */
 224/* #define CONFIG_SYS_PCI_SUBSYS_ID     CONFIG_SYS_PCI_SUBSYS_DEVICEID */
 225
 226/*
 227 *  NETWORK Support (PCI):
 228 */
 229/* Support for Intel 82557/82559/82559ER chips. */
 230#define CONFIG_EEPRO100
 231
 232/*-----------------------------------------------------------------------
 233 * Xilinx System ACE support
 234 *----------------------------------------------------------------------*/
 235#define CONFIG_SYSTEMACE        1       /* Enable SystemACE support     */
 236#define CONFIG_SYS_SYSTEMACE_WIDTH      16      /* Data bus width is 16         */
 237#define CONFIG_SYS_SYSTEMACE_BASE       CONFIG_SYS_ACE_BASE
 238
 239/*-----------------------------------------------------------------------
 240 * External Bus Controller (EBC) Setup
 241 *----------------------------------------------------------------------*/
 242
 243/* Memory Bank 0 (Flash) initialization                                 */
 244#define CONFIG_SYS_EBC_PB0AP            (EBC_BXAP_BME_DISABLED      |           \
 245                                 EBC_BXAP_TWT_ENCODE(7)     |           \
 246                                 EBC_BXAP_BCE_DISABLE       |           \
 247                                 EBC_BXAP_BCT_2TRANS        |           \
 248                                 EBC_BXAP_CSN_ENCODE(0)     |           \
 249                                 EBC_BXAP_OEN_ENCODE(0)     |           \
 250                                 EBC_BXAP_WBN_ENCODE(0)     |           \
 251                                 EBC_BXAP_WBF_ENCODE(0)     |           \
 252                                 EBC_BXAP_TH_ENCODE(0)      |           \
 253                                 EBC_BXAP_RE_DISABLED       |           \
 254                                 EBC_BXAP_SOR_DELAYED       |           \
 255                                 EBC_BXAP_BEM_WRITEONLY     |           \
 256                                 EBC_BXAP_PEN_DISABLED)
 257#define CONFIG_SYS_EBC_PB0CR            (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) |   \
 258                                 EBC_BXCR_BS_16MB                    |  \
 259                                 EBC_BXCR_BU_RW                      |  \
 260                                 EBC_BXCR_BW_16BIT)
 261
 262/* Memory Bank 1 (Xilinx System ACE controller) initialization          */
 263#define CONFIG_SYS_EBC_PB1AP            (EBC_BXAP_BME_DISABLED      |           \
 264                                 EBC_BXAP_TWT_ENCODE(4)     |           \
 265                                 EBC_BXAP_BCE_DISABLE       |           \
 266                                 EBC_BXAP_BCT_2TRANS        |           \
 267                                 EBC_BXAP_CSN_ENCODE(0)     |           \
 268                                 EBC_BXAP_OEN_ENCODE(0)     |           \
 269                                 EBC_BXAP_WBN_ENCODE(0)     |           \
 270                                 EBC_BXAP_WBF_ENCODE(0)     |           \
 271                                 EBC_BXAP_TH_ENCODE(0)      |           \
 272                                 EBC_BXAP_RE_DISABLED       |           \
 273                                 EBC_BXAP_SOR_NONDELAYED    |           \
 274                                 EBC_BXAP_BEM_WRITEONLY     |           \
 275                                 EBC_BXAP_PEN_DISABLED)
 276#define CONFIG_SYS_EBC_PB1CR            (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_ACE_BASE)  |    \
 277                                 EBC_BXCR_BS_1MB                    |   \
 278                                 EBC_BXCR_BU_RW                     |   \
 279                                 EBC_BXCR_BW_16BIT)
 280
 281/*-------------------------------------------------------------------------
 282 * Initialize EBC CONFIG -
 283 * Keep the Default value, but the bit PDT which has to be set to 1 ?TBC
 284 * default value : 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000
 285 *-------------------------------------------------------------------------*/
 286#define CONFIG_SYS_EBC_CFG              (EBC_CFG_LE_UNLOCK    | \
 287                                 EBC_CFG_PTD_ENABLE   | \
 288                                 EBC_CFG_RTC_16PERCLK | \
 289                                 EBC_CFG_ATC_PREVIOUS | \
 290                                 EBC_CFG_DTC_PREVIOUS | \
 291                                 EBC_CFG_CTC_PREVIOUS | \
 292                                 EBC_CFG_OEO_PREVIOUS | \
 293                                 EBC_CFG_EMC_DEFAULT  | \
 294                                 EBC_CFG_PME_DISABLE  | \
 295                                 EBC_CFG_PR_16)
 296
 297/*-----------------------------------------------------------------------
 298 * GPIO Setup
 299 *----------------------------------------------------------------------*/
 300#define CONFIG_SYS_GPIO_PCIE_PRESENT0   17
 301#define CONFIG_SYS_GPIO_PCIE_PRESENT1   21
 302#define CONFIG_SYS_GPIO_PCIE_PRESENT2   23
 303#define CONFIG_SYS_GPIO_RS232_FORCEOFF  30
 304
 305#define CONFIG_SYS_PFC0         (GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT0) | \
 306                                 GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT1) | \
 307                                 GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT2) | \
 308                                 GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF))
 309#define CONFIG_SYS_GPIO_OR              GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF)
 310#define CONFIG_SYS_GPIO_TCR             GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF)
 311#define CONFIG_SYS_GPIO_ODR             0
 312
 313#endif  /* __CONFIG_H */
 314