LXR uboot/include/configs/kilauea.h

   1/*
   2 * Copyright (c) 2008 Nuovation System Designs, LLC
   3 *   Grant Erickson <gerickson@nuovations.com>
   4 *
   5 * (C) Copyright 2007
   6 * Stefan Roese, DENX Software Engineering, sr@denx.de.
   7 *
   8 * SPDX-License-Identifier:     GPL-2.0+
   9 */
  10
  11/************************************************************************
  12 * kilauea.h - configuration for AMCC Kilauea (405EX)
  13 ***********************************************************************/
  14
  15#ifndef __CONFIG_H
  16#define __CONFIG_H
  17
  18/*-----------------------------------------------------------------------
  19 * High Level Configuration Options
  20 *----------------------------------------------------------------------*/
  21#define CONFIG_KILAUEA          1               /* Board is Kilauea     */
  22#define CONFIG_405EX            1               /* Specifc 405EX support*/
  23#define CONFIG_SYS_CLK_FREQ     33333333        /* ext frequency to pll */
  24
  25#ifndef CONFIG_SYS_TEXT_BASE
  26#define CONFIG_SYS_TEXT_BASE    0xFFFA0000
  27#endif
  28
  29/*
  30 * CHIP_21 errata - you must set this to match your exact CPU, else your
  31 * board will not boot.  DO NOT enable this unless you have JTAG available
  32 * for recovery, in the event you get it wrong.
  33 *
  34 * Kilauea uses the 405EX, while Haleakala uses the 405EXr.  Either board
  35 * may be equipped for security or not.  You must look at the CPU part
  36 * number to be sure what you have.
  37 */
  38/* #define CONFIG_SYS_4xx_CHIP_21_405EX_NO_SECURITY */
  39/* #define CONFIG_SYS_4xx_CHIP_21_405EX_SECURITY */
  40/* #define CONFIG_SYS_4xx_CHIP_21_405EXr_NO_SECURITY */
  41/* #define CONFIG_SYS_4xx_CHIP_21_405EXr_SECURITY */
  42
  43/*
  44 * Include common defines/options for all AMCC eval boards
  45 */
  46#define CONFIG_HOSTNAME         kilauea
  47#include "amcc-common.h"
  48
  49#define CONFIG_MISC_INIT_R      1               /* Call misc_init_r     */
  50#define CONFIG_BOARD_TYPES
  51#define CONFIG_BOARD_EMAC_COUNT
  52
  53/*-----------------------------------------------------------------------
  54 * Base addresses -- Note these are effective addresses where the
  55 * actual resources get mapped (not physical addresses)
  56 *----------------------------------------------------------------------*/
  57#define CONFIG_SYS_FLASH_BASE           0xFC000000
  58#define CONFIG_SYS_NAND_ADDR            0xF8000000
  59#define CONFIG_SYS_FPGA_BASE            0xF0000000
  60
  61/*-----------------------------------------------------------------------
  62 * Initial RAM & Stack Pointer Configuration Options
  63 *
  64 *   There are traditionally three options for the primordial
  65 *   (i.e. initial) stack usage on the 405-series:
  66 *
  67 *      1) On-chip Memory (OCM) (i.e. SRAM)
  68 *      2) Data cache
  69 *      3) SDRAM
  70 *
  71 *   For the 405EX(r), there is no OCM, so we are left with (2) or (3)
  72 *   the latter of which is less than desireable since it requires
  73 *   setting up the SDRAM and ECC in assembly code.
  74 *
  75 *   To use (2), define 'CONFIG_SYS_INIT_DCACHE_CS' to be an unused chip
  76 *   select on the External Bus Controller (EBC) and then select a
  77 *   value for 'CONFIG_SYS_INIT_RAM_ADDR' outside of the range of valid,
  78 *   physical SDRAM. Otherwise, undefine 'CONFIG_SYS_INIT_DCACHE_CS' and
  79 *   select a value for 'CONFIG_SYS_INIT_RAM_ADDR' within the range of valid,
  80 *   physical SDRAM to use (3).
  81 *-----------------------------------------------------------------------*/
  82
  83#define CONFIG_SYS_INIT_DCACHE_CS       4
  84
  85#if defined(CONFIG_SYS_INIT_DCACHE_CS)
  86#define CONFIG_SYS_INIT_RAM_ADDR        (CONFIG_SYS_SDRAM_BASE + ( 1 << 30))    /*  1 GiB */
  87#else
  88#define CONFIG_SYS_INIT_RAM_ADDR        (CONFIG_SYS_SDRAM_BASE + (32 << 20))    /* 32 MiB */
  89#endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
  90
  91#define CONFIG_SYS_INIT_RAM_SIZE        (4 << 10)                       /*  4 KiB */
  92#define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  93
  94/*
  95 * If the data cache is being used for the primordial stack and global
  96 * data area, the POST word must be placed somewhere else. The General
  97 * Purpose Timer (GPT) is unused by u-boot and the kernel and preserves
  98 * its compare and mask register contents across reset, so it is used
  99 * for the POST word.
 100 */
 101
 102#if defined(CONFIG_SYS_INIT_DCACHE_CS)
 103# define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
 104# define CONFIG_SYS_POST_WORD_ADDR      (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6)
 105#else
 106# define CONFIG_SYS_INIT_EXTRA_SIZE     16
 107# define CONFIG_SYS_INIT_SP_OFFSET      (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_EXTRA_SIZE)
 108# define CONFIG_SYS_OCM_DATA_ADDR       CONFIG_SYS_INIT_RAM_ADDR
 109#endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
 110
 111/*-----------------------------------------------------------------------
 112 * Serial Port
 113 *----------------------------------------------------------------------*/
 114#define CONFIG_SYS_EXT_SERIAL_CLOCK     11059200        /* ext. 11.059MHz clk   */
 115#define CONFIG_CONS_INDEX       1       /* Use UART0                    */
 116
 117/*-----------------------------------------------------------------------
 118 * Environment
 119 *----------------------------------------------------------------------*/
 120#define CONFIG_ENV_IS_IN_FLASH     1    /* use FLASH for environment vars       */
 121
 122/*-----------------------------------------------------------------------
 123 * FLASH related
 124 *----------------------------------------------------------------------*/
 125#define CONFIG_SYS_FLASH_CFI                    /* The flash is CFI compatible  */
 126#define CONFIG_FLASH_CFI_DRIVER         /* Use common CFI driver        */
 127
 128#define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE}
 129#define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 130#define CONFIG_SYS_MAX_FLASH_SECT       512     /* max number of sectors on one chip    */
 131
 132#define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 133#define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 134
 135#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster)     */
 136#define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
 137
 138#ifdef CONFIG_ENV_IS_IN_FLASH
 139#define CONFIG_ENV_SECT_SIZE    0x20000 /* size of one complete sector  */
 140#define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
 141#define CONFIG_ENV_SIZE         0x4000  /* Total Size of Environment Sector     */
 142
 143/* Address and size of Redundant Environment Sector     */
 144#define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
 145#define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 146#endif /* CONFIG_ENV_IS_IN_FLASH */
 147
 148/*-----------------------------------------------------------------------
 149 * NAND FLASH
 150 *----------------------------------------------------------------------*/
 151#define CONFIG_SYS_MAX_NAND_DEVICE      1
 152#define CONFIG_SYS_NAND_BASE            (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
 153#define CONFIG_SYS_NAND_SELECT_DEVICE  1        /* nand driver supports mutipl. chips   */
 154
 155/*-----------------------------------------------------------------------
 156 * DDR SDRAM
 157 *----------------------------------------------------------------------*/
 158#define CONFIG_SYS_MBYTES_SDRAM        (256)            /* 256MB                        */
 159
 160/*
 161 * CONFIG_PPC4xx_DDR_AUTOCALIBRATION
 162 *
 163 * Note: DDR Autocalibration Method_A scans the full range of possible PPC4xx
 164 *       SDRAM Controller DDR autocalibration values and takes a lot longer
 165 *       to run than Method_B.
 166 * (See the Method_A and Method_B algorithm discription in the file:
 167 *      arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c)
 168 * Define CONFIG_PPC4xx_DDR_METHOD_A to use DDR autocalibration Method_A
 169 *
 170 * DDR Autocalibration Method_B is the default.
 171 */
 172#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION       /* IBM DDR autocalibration */
 173#define DEBUG_PPC4xx_DDR_AUTOCALIBRATION        /* dynamic DDR autocal debug */
 174#undef  CONFIG_PPC4xx_DDR_METHOD_A
 175
 176#define CONFIG_SYS_SDRAM0_MB0CF_BASE    ((  0 << 20) + CONFIG_SYS_SDRAM_BASE)
 177
 178/* DDR1/2 SDRAM Device Control Register Data Values */
 179#define CONFIG_SYS_SDRAM0_MB0CF ((CONFIG_SYS_SDRAM0_MB0CF_BASE >> 3)    | \
 180                                 SDRAM_RXBAS_SDSZ_256MB         | \
 181                                 SDRAM_RXBAS_SDAM_MODE7         | \
 182                                 SDRAM_RXBAS_SDBE_ENABLE)
 183#define CONFIG_SYS_SDRAM0_MB1CF SDRAM_RXBAS_SDBE_DISABLE
 184#define CONFIG_SYS_SDRAM0_MB2CF SDRAM_RXBAS_SDBE_DISABLE
 185#define CONFIG_SYS_SDRAM0_MB3CF SDRAM_RXBAS_SDBE_DISABLE
 186#define CONFIG_SYS_SDRAM0_MCOPT1        (SDRAM_MCOPT1_PMU_OPEN          | \
 187                                 SDRAM_MCOPT1_8_BANKS           | \
 188                                 SDRAM_MCOPT1_DDR2_TYPE         | \
 189                                 SDRAM_MCOPT1_QDEP              | \
 190                                 SDRAM_MCOPT1_DCOO_DISABLED)
 191#define CONFIG_SYS_SDRAM0_MCOPT2        0x00000000
 192#define CONFIG_SYS_SDRAM0_MODT0 (SDRAM_MODT_EB0W_ENABLE | \
 193                                 SDRAM_MODT_EB0R_ENABLE)
 194#define CONFIG_SYS_SDRAM0_MODT1 0x00000000
 195#define CONFIG_SYS_SDRAM0_CODT          (SDRAM_CODT_RK0R_ON             | \
 196                                 SDRAM_CODT_CKLZ_36OHM          | \
 197                                 SDRAM_CODT_DQS_1_8_V_DDR2      | \
 198                                 SDRAM_CODT_IO_NMODE)
 199#define CONFIG_SYS_SDRAM0_RTR           SDRAM_RTR_RINT_ENCODE(1560)
 200#define CONFIG_SYS_SDRAM0_INITPLR0      (SDRAM_INITPLR_ENABLE                   | \
 201                SDRAM_INITPLR_IMWT_ENCODE(80)                           | \
 202                SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_NOP))
 203#define CONFIG_SYS_SDRAM0_INITPLR1      (SDRAM_INITPLR_ENABLE                   | \
 204                SDRAM_INITPLR_IMWT_ENCODE(3)                            | \
 205                SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE)          | \
 206                SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR)                   | \
 207                SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
 208#define CONFIG_SYS_SDRAM0_INITPLR2      (SDRAM_INITPLR_ENABLE                   | \
 209                SDRAM_INITPLR_IMWT_ENCODE(2)                            | \
 210                SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                | \
 211                SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR2)                 | \
 212                SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR2_TEMP_COMMERCIAL))
 213#define CONFIG_SYS_SDRAM0_INITPLR3      (SDRAM_INITPLR_ENABLE                   | \
 214                SDRAM_INITPLR_IMWT_ENCODE(2)                            | \
 215                SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                | \
 216                SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR3)                 | \
 217                SDRAM_INITPLR_IMA_ENCODE(0))
 218#define CONFIG_SYS_SDRAM0_INITPLR4      (SDRAM_INITPLR_ENABLE                   | \
 219                SDRAM_INITPLR_IMWT_ENCODE(2)                            | \
 220                SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                | \
 221                SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR)                  | \
 222                SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_DQS_DISABLE | \
 223                                         JEDEC_MA_EMR_RTT_75OHM))
 224#define CONFIG_SYS_SDRAM0_INITPLR5      (SDRAM_INITPLR_ENABLE                   | \
 225                SDRAM_INITPLR_IMWT_ENCODE(2)                            | \
 226                SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                | \
 227                SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR)                   | \
 228                SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
 229                                         JEDEC_MA_MR_CL_DDR2_4_0_CLK | \
 230                                         JEDEC_MA_MR_BLEN_4 | \
 231                                         JEDEC_MA_MR_DLL_RESET))
 232#define CONFIG_SYS_SDRAM0_INITPLR6      (SDRAM_INITPLR_ENABLE                   | \
 233                SDRAM_INITPLR_IMWT_ENCODE(3)                            | \
 234                SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE)          | \
 235                SDRAM_INITPLR_IBA_ENCODE(0x0)                           | \
 236                SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
 237#define CONFIG_SYS_SDRAM0_INITPLR7      (SDRAM_INITPLR_ENABLE                   | \
 238                SDRAM_INITPLR_IMWT_ENCODE(26)                           | \
 239                SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
 240#define CONFIG_SYS_SDRAM0_INITPLR8      (SDRAM_INITPLR_ENABLE                   | \
 241                SDRAM_INITPLR_IMWT_ENCODE(26)                           | \
 242                SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
 243#define CONFIG_SYS_SDRAM0_INITPLR9      (SDRAM_INITPLR_ENABLE                   | \
 244                SDRAM_INITPLR_IMWT_ENCODE(26)                           | \
 245                SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
 246#define CONFIG_SYS_SDRAM0_INITPLR10     (SDRAM_INITPLR_ENABLE                   | \
 247                SDRAM_INITPLR_IMWT_ENCODE(26)                           | \
 248                SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
 249#define CONFIG_SYS_SDRAM0_INITPLR11     (SDRAM_INITPLR_ENABLE                   | \
 250                SDRAM_INITPLR_IMWT_ENCODE(2)                            | \
 251                SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                | \
 252                SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR)                   | \
 253                SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
 254                                         JEDEC_MA_MR_CL_DDR2_4_0_CLK | \
 255                                         JEDEC_MA_MR_BLEN_4))
 256#define CONFIG_SYS_SDRAM0_INITPLR12     (SDRAM_INITPLR_ENABLE                   | \
 257                SDRAM_INITPLR_IMWT_ENCODE(2)                            | \
 258                SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                | \
 259                SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR)                  | \
 260                SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_ENTER | \
 261                                         JEDEC_MA_EMR_RDQS_DISABLE | \
 262                                         JEDEC_MA_EMR_DQS_DISABLE | \
 263                                         JEDEC_MA_EMR_RTT_DISABLED | \
 264                                         JEDEC_MA_EMR_ODS_NORMAL))
 265#define CONFIG_SYS_SDRAM0_INITPLR13     (SDRAM_INITPLR_ENABLE                   | \
 266                SDRAM_INITPLR_IMWT_ENCODE(2)                            | \
 267                SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                | \
 268                SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR)                  | \
 269                SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_EXIT | \
 270                                         JEDEC_MA_EMR_RDQS_DISABLE | \
 271                                         JEDEC_MA_EMR_DQS_DISABLE | \
 272                                         JEDEC_MA_EMR_RTT_DISABLED | \
 273                                         JEDEC_MA_EMR_ODS_NORMAL))
 274#define CONFIG_SYS_SDRAM0_INITPLR14     (SDRAM_INITPLR_DISABLE)
 275#define CONFIG_SYS_SDRAM0_INITPLR15     (SDRAM_INITPLR_DISABLE)
 276#define CONFIG_SYS_SDRAM0_RQDC          (SDRAM_RQDC_RQDE_ENABLE | \
 277                                 SDRAM_RQDC_RQFD_ENCODE(56))
 278#define CONFIG_SYS_SDRAM0_RFDC          SDRAM_RFDC_RFFD_ENCODE(521)
 279#define CONFIG_SYS_SDRAM0_RDCC          (SDRAM_RDCC_RDSS_T2)
 280#define CONFIG_SYS_SDRAM0_DLCR          (SDRAM_DLCR_DCLM_AUTO           | \
 281                                 SDRAM_DLCR_DLCS_CONT_DONE      | \
 282                                 SDRAM_DLCR_DLCV_ENCODE(165))
 283#define CONFIG_SYS_SDRAM0_CLKTR (SDRAM_CLKTR_CLKP_180_DEG_ADV)
 284#define CONFIG_SYS_SDRAM0_WRDTR 0x00000000
 285#define CONFIG_SYS_SDRAM0_SDTR1 (SDRAM_SDTR1_LDOF_2_CLK | \
 286                                 SDRAM_SDTR1_RTW_2_CLK  | \
 287                                 SDRAM_SDTR1_RTRO_1_CLK)
 288#define CONFIG_SYS_SDRAM0_SDTR2 (SDRAM_SDTR2_RCD_3_CLK          | \
 289                                 SDRAM_SDTR2_WTR_2_CLK          | \
 290                                 SDRAM_SDTR2_XSNR_32_CLK        | \
 291                                 SDRAM_SDTR2_WPC_4_CLK          | \
 292                                 SDRAM_SDTR2_RPC_2_CLK          | \
 293                                 SDRAM_SDTR2_RP_3_CLK           | \
 294                                 SDRAM_SDTR2_RRD_2_CLK)
 295#define CONFIG_SYS_SDRAM0_SDTR3 (SDRAM_SDTR3_RAS_ENCODE(8)      | \
 296                                 SDRAM_SDTR3_RC_ENCODE(11)      | \
 297                                 SDRAM_SDTR3_XCS                | \
 298                                 SDRAM_SDTR3_RFC_ENCODE(26))
 299#define CONFIG_SYS_SDRAM0_MMODE (SDRAM_MMODE_WR_DDR2_3_CYC | \
 300                                 SDRAM_MMODE_DCL_DDR2_4_0_CLK | \
 301                                 SDRAM_MMODE_BLEN_4)
 302#define CONFIG_SYS_SDRAM0_MEMODE        (SDRAM_MEMODE_DQS_DISABLE | \
 303                                 SDRAM_MEMODE_RTT_75OHM)
 304
 305/*-----------------------------------------------------------------------
 306 * I2C
 307 *----------------------------------------------------------------------*/
 308#define CONFIG_SYS_I2C_PPC4XX_SPEED_0           400000
 309
 310#define CONFIG_SYS_I2C_EEPROM_ADDR      0x52    /* I2C boot EEPROM (24C02BN)    */
 311#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1       /* Bytes of address             */
 312#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 313#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10
 314
 315/* I2C bootstrap EEPROM */
 316#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR       0x52
 317#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET     0
 318#define CONFIG_4xx_CONFIG_BLOCKSIZE             16
 319
 320/* Standard DTT sensor configuration */
 321#define CONFIG_DTT_DS1775       1
 322#define CONFIG_DTT_SENSORS      { 0 }
 323#define CONFIG_SYS_I2C_DTT_ADDR 0x48
 324
 325/* RTC configuration */
 326#define CONFIG_RTC_DS1338       1
 327#define CONFIG_SYS_I2C_RTC_ADDR 0x68
 328
 329/*-----------------------------------------------------------------------
 330 * Ethernet
 331 *----------------------------------------------------------------------*/
 332#define CONFIG_M88E1111_PHY     1
 333#define CONFIG_IBM_EMAC4_V4     1
 334#define CONFIG_EMAC_PHY_MODE    EMAC_PHY_MODE_RGMII_RGMII
 335#define CONFIG_PHY_ADDR         1       /* PHY address, See schematics  */
 336
 337#define CONFIG_PHY_RESET        1       /* reset phy upon startup       */
 338#define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 339
 340#define CONFIG_HAS_ETH0         1
 341
 342#define CONFIG_HAS_ETH1         1       /* add support for "eth1addr"   */
 343#define CONFIG_PHY1_ADDR        2
 344
 345/* Debug messages for the DDR autocalibration */
 346#define CONFIG_AUTOCALIB                "silent\0"  /* default is non-verbose */
 347
 348/*
 349 * Default environment variables
 350 */
 351#define CONFIG_EXTRA_ENV_SETTINGS                                       \
 352        CONFIG_AMCC_DEF_ENV                                             \
 353        CONFIG_AMCC_DEF_ENV_POWERPC                                     \
 354        CONFIG_AMCC_DEF_ENV_PPC_OLD                                     \
 355        CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
 356        "logversion=2\0"                                                \
 357        "kernel_addr=fc000000\0"                                        \
 358        "fdt_addr=fc1e0000\0"                                           \
 359        "ramdisk_addr=fc200000\0"                                       \
 360        "pciconfighost=1\0"                                             \
 361        "pcie_mode=RP:RP\0"                                             \
 362        ""
 363
 364/*
 365 * Commands additional to the ones defined in amcc-common.h
 366 */
 367#define CONFIG_CMD_NAND
 368#define CONFIG_CMD_PCI
 369
 370#define CONFIG_SYS_POST_MEMORY_ON       CONFIG_SYS_POST_MEMORY
 371
 372/* POST support */
 373#define CONFIG_POST             (CONFIG_SYS_POST_CACHE          | \
 374                                 CONFIG_SYS_POST_CPU            | \
 375                                 CONFIG_SYS_POST_ETHER          | \
 376                                 CONFIG_SYS_POST_I2C            | \
 377                                 CONFIG_SYS_POST_MEMORY_ON      | \
 378                                 CONFIG_SYS_POST_UART)
 379
 380/* Define here the base-addresses of the UARTs to test in POST */
 381#define CONFIG_SYS_POST_UART_TABLE      { CONFIG_SYS_NS16550_COM1, \
 382                        CONFIG_SYS_NS16550_COM2 }
 383
 384#define CONFIG_LOGBUFFER
 385#define CONFIG_SYS_POST_CACHE_ADDR      0x00800000 /* free virtual address      */
 386
 387/*-----------------------------------------------------------------------
 388 * PCI stuff
 389 *----------------------------------------------------------------------*/
 390#define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 391#define CONFIG_PCI_SCAN_SHOW    1       /* show pci devices on startup  */
 392#define CONFIG_PCI_CONFIG_HOST_BRIDGE
 393
 394/*-----------------------------------------------------------------------
 395 * PCIe stuff
 396 *----------------------------------------------------------------------*/
 397#define CONFIG_SYS_PCIE_MEMBASE 0x90000000      /* mapped PCIe memory   */
 398#define CONFIG_SYS_PCIE_MEMSIZE 0x08000000      /* 128 Meg, smallest incr per port */
 399
 400#define CONFIG_SYS_PCIE0_CFGBASE        0xa0000000      /* remote access */
 401#define CONFIG_SYS_PCIE0_XCFGBASE       0xb0000000      /* local access */
 402#define CONFIG_SYS_PCIE0_CFGMASK        0xe0000001      /* 512 Meg */
 403
 404#define CONFIG_SYS_PCIE1_CFGBASE        0xc0000000      /* remote access */
 405#define CONFIG_SYS_PCIE1_XCFGBASE       0xd0000000      /* local access */
 406#define CONFIG_SYS_PCIE1_CFGMASK        0xe0000001      /* 512 Meg */
 407
 408#define CONFIG_SYS_PCIE0_UTLBASE        0xef502000
 409#define CONFIG_SYS_PCIE1_UTLBASE        0xef503000
 410
 411/* base address of inbound PCIe window */
 412#define CONFIG_SYS_PCIE_INBOUND_BASE    0x0000000000000000ULL
 413
 414/*-----------------------------------------------------------------------
 415 * External Bus Controller (EBC) Setup
 416 *----------------------------------------------------------------------*/
 417#define CONFIG_SYS_NAND_CS              1               /* NAND chip connected to CSx   */
 418
 419/* Memory Bank 0 (NOR-FLASH) initialization                                     */
 420#define CONFIG_SYS_EBC_PB0AP            0x05806500
 421#define CONFIG_SYS_EBC_PB0CR           0xFC0DA000  /* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit*/
 422
 423/* Memory Bank 1 (NAND-FLASH) initialization                                    */
 424#define CONFIG_SYS_EBC_PB1AP            0x018003c0
 425#define CONFIG_SYS_EBC_PB1CR            (CONFIG_SYS_NAND_ADDR | 0x1e000)
 426
 427/* Memory Bank 2 (FPGA) initialization                                  */
 428#define CONFIG_SYS_EBC_PB2AP            (EBC_BXAP_BME_ENABLED |         \
 429                                         EBC_BXAP_FWT_ENCODE(6) |       \
 430                                         EBC_BXAP_BWT_ENCODE(1) |       \
 431                                         EBC_BXAP_BCE_DISABLE |         \
 432                                         EBC_BXAP_BCT_2TRANS |          \
 433                                         EBC_BXAP_CSN_ENCODE(0) |       \
 434                                         EBC_BXAP_OEN_ENCODE(0) |       \
 435                                         EBC_BXAP_WBN_ENCODE(3) |       \
 436                                         EBC_BXAP_WBF_ENCODE(1) |       \
 437                                         EBC_BXAP_TH_ENCODE(4) |        \
 438                                         EBC_BXAP_RE_DISABLED |         \
 439                                         EBC_BXAP_SOR_DELAYED |         \
 440                                         EBC_BXAP_BEM_WRITEONLY |       \
 441                                         EBC_BXAP_PEN_DISABLED)
 442#define CONFIG_SYS_EBC_PB2CR    (CONFIG_SYS_FPGA_BASE | 0x18000)
 443
 444#define CONFIG_SYS_EBC_CFG              0x7FC00000 /*  EBC0_CFG */
 445
 446/*-----------------------------------------------------------------------
 447 * GPIO Setup
 448 *----------------------------------------------------------------------*/
 449#define CONFIG_SYS_4xx_GPIO_TABLE { /*    Out             GPIO  Alternate1      Alternate2      Alternate3 */ \
 450{                                                                                       \
 451/* GPIO Core 0 */                                                                       \
 452{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO0 EBC_DATA_PAR(0)                 */      \
 453{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO1 EBC_DATA_PAR(1)                 */      \
 454{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO2 EBC_DATA_PAR(2)                 */      \
 455{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO3 EBC_DATA_PAR(3)                 */      \
 456{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO4 EBC_DATA(20)    USB2_DATA(4)    */      \
 457{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO5 EBC_DATA(21)    USB2_DATA(5)    */      \
 458{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO6 EBC_DATA(22)    USB2_DATA(6)    */      \
 459{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO7 EBC_DATA(23)    USB2_DATA(7)    */      \
 460{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 CS(1)/NFCE(1)   IRQ(7)          */      \
 461{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 CS(2)/NFCE(2)   IRQ(8)          */      \
 462{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 CS(3)/NFCE(3)  IRQ(9)          */      \
 463{GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 IRQ(6)                         */      \
 464{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO12 EBC_DATA(16)   USB2_DATA(0)    */      \
 465{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO13 EBC_DATA(17)   USB2_DATA(1)    */      \
 466{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO14 EBC_DATA(18)   USB2_DATA(2)    */      \
 467{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO15 EBC_DATA(19)   USB2_DATA(3)    */      \
 468{GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 UART0_DCD      UART1_CTS       */      \
 469{GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 UART0_DSR      UART1_RTS       */      \
 470{GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 UART0_CTS                      */      \
 471{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 UART0_RTS                      */      \
 472{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO20 UART0_DTR      UART1_TX        */      \
 473{GPIO0_BASE, GPIO_IN,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO21 UART0_RI       UART1_RX        */      \
 474{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO22 EBC_HOLD_REQ   DMA_ACK2        */      \
 475{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO23 EBC_HOLD_ACK   DMA_REQ2        */      \
 476{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO24 EBC_EXT_REQ    DMA_EOT2        IRQ(4) */ \
 477{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO25 EBC_EXT_ACK    DMA_ACK3        IRQ(3) */ \
 478{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 EBC_ADDR(5)    DMA_EOT0        TS(3) */ \
 479{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO27 EBC_BUS_REQ    DMA_EOT3        IRQ(5) */ \
 480{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO28                                */      \
 481{GPIO0_BASE, GPIO_IN,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO29 DMA_EOT1       IRQ(2)          */      \
 482{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO30 DMA_REQ1       IRQ(1)          */      \
 483{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO31 DMA_ACK1       IRQ(0)          */      \
 484}                                                                                               \
 485}
 486
 487/*-----------------------------------------------------------------------
 488 * Some Kilauea stuff..., mainly fpga registers
 489 */
 490#define CONFIG_SYS_FPGA_REG_BASE                CONFIG_SYS_FPGA_BASE
 491#define CONFIG_SYS_FPGA_FIFO_BASE               (CONFIG_SYS_FPGA_BASE | (1 << 10))
 492
 493/* interrupt */
 494#define CONFIG_SYS_FPGA_SLIC0_R_DPRAM_INT       0x80000000
 495#define CONFIG_SYS_FPGA_SLIC0_W_DPRAM_INT       0x40000000
 496#define CONFIG_SYS_FPGA_SLIC1_R_DPRAM_INT       0x20000000
 497#define CONFIG_SYS_FPGA_SLIC1_W_DPRAM_INT       0x10000000
 498#define CONFIG_SYS_FPGA_PHY0_INT                0x08000000
 499#define CONFIG_SYS_FPGA_PHY1_INT                0x04000000
 500#define CONFIG_SYS_FPGA_SLIC0_INT               0x02000000
 501#define CONFIG_SYS_FPGA_SLIC1_INT               0x01000000
 502
 503/* DPRAM setting */
 504/* 00: 32B; 01: 64B; 10: 128B; 11: 256B  */
 505#define CONFIG_SYS_FPGA_DPRAM_R_INT_LINE        0x00400000      /* 64 B */
 506#define CONFIG_SYS_FPGA_DPRAM_W_INT_LINE        0x00100000      /* 64 B */
 507#define CONFIG_SYS_FPGA_DPRAM_RW_TYPE           0x00080000
 508#define CONFIG_SYS_FPGA_DPRAM_RST               0x00040000
 509#define CONFIG_SYS_FPGA_UART0_FO                0x00020000
 510#define CONFIG_SYS_FPGA_UART1_FO                0x00010000
 511
 512/* loopback */
 513#define CONFIG_SYS_FPGA_CHIPSIDE_LOOPBACK       0x00004000
 514#define CONFIG_SYS_FPGA_LINESIDE_LOOPBACK       0x00008000
 515#define CONFIG_SYS_FPGA_SLIC0_ENABLE            0x00002000
 516#define CONFIG_SYS_FPGA_SLIC1_ENABLE            0x00001000
 517#define CONFIG_SYS_FPGA_SLIC0_CS                0x00000800
 518#define CONFIG_SYS_FPGA_SLIC1_CS                0x00000400
 519#define CONFIG_SYS_FPGA_USER_LED0               0x00000200
 520#define CONFIG_SYS_FPGA_USER_LED1               0x00000100
 521
 522#define CONFIG_SYS_FPGA_MAGIC_MASK              0xffff0000
 523#define CONFIG_SYS_FPGA_MAGIC                   0xabcd0000
 524#define CONFIG_SYS_FPGA_VER_MASK                0x0000ff00
 525
 526#endif  /* __CONFIG_H */
 527