LXR uboot/include/configs/km82xx.h

   1/*
   2 * (C) Copyright 2007-2011
   3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
   4 *
   5 * SPDX-License-Identifier:     GPL-2.0+
   6 */
   7
   8#ifndef __CONFIG_H
   9#define __CONFIG_H
  10
  11/*
  12 * High Level Configuration Options
  13 * (easy to change)
  14 */
  15
  16#define CONFIG_MPC8247
  17/* MGCOGE */
  18#if defined(CONFIG_MGCOGE)
  19#define CONFIG_HOSTNAME         mgcoge
  20#define CONFIG_KM_BOARD_EXTRA_ENV       ""
  21
  22/* MGCOGE3NE */
  23#elif defined(CONFIG_MGCOGE3NE)
  24#define CONFIG_HOSTNAME         mgcoge3ne
  25#define CONFIG_KM_82XX
  26#define CONFIG_KM_BOARD_EXTRA_ENV       "bobcatreset=true\0"
  27
  28#else
  29#error ("Board unsupported")
  30#endif
  31
  32#define CONFIG_SYS_TEXT_BASE    0xFE000000
  33
  34#define CONFIG_MISC_INIT_R
  35
  36/* include common defines/options for all Keymile boards */
  37#include "km/keymile-common.h"
  38#include "km/km-powerpc.h"
  39
  40#define CONFIG_SYS_SDRAM_BASE           0x00000000
  41#define CONFIG_SYS_FLASH_BASE           0xFE000000
  42#define CONFIG_SYS_FLASH_SIZE           32
  43#define CONFIG_SYS_FLASH_CFI
  44#define CONFIG_FLASH_CFI_DRIVER
  45
  46/* MGCOGE */
  47#if defined(CONFIG_MGCOGE)
  48#define CONFIG_SYS_MAX_FLASH_BANKS      3
  49/* max num of sects on one chip */
  50#define CONFIG_SYS_MAX_FLASH_SECT       512
  51
  52#define CONFIG_SYS_FLASH_BASE_1 0x50000000
  53#define CONFIG_SYS_FLASH_SIZE_1 32
  54#define CONFIG_SYS_FLASH_BASE_2 0x52000000
  55#define CONFIG_SYS_FLASH_SIZE_2 32
  56
  57#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \
  58                                        CONFIG_SYS_FLASH_BASE_1, \
  59                                        CONFIG_SYS_FLASH_BASE_2 }
  60#define MTDIDS_DEFAULT          "nor3=app"
  61
  62/*
  63 * Bank 1 - 60x bus SDRAM
  64 */
  65#define SDRAM_MAX_SIZE  0x08000000                      /* max. 128 MB  */
  66#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT   (256 << 20)     /* less than 256 MB */
  67
  68/* SDRAM initialization values
  69*/
  70
  71#define CONFIG_SYS_OR1  ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & \
  72                           ORxS_SDAM_MSK)               |\
  73                        ORxS_BPD_8                      |\
  74                        ORxS_ROWST_PBI0_A7              |\
  75                        ORxS_NUMR_13)
  76
  77#define CONFIG_SYS_PSDMR (                              \
  78                        PSDMR_SDAM_A14_IS_A5            |\
  79                        PSDMR_BSMA_A14_A16              |\
  80                        PSDMR_SDA10_PBI0_A9             |\
  81                        PSDMR_RFRC_5_CLK                |\
  82                        PSDMR_PRETOACT_2W               |\
  83                        PSDMR_ACTTORW_2W                |\
  84                        PSDMR_LDOTOPRE_1C               |\
  85                        PSDMR_WRC_1C                    |\
  86                        PSDMR_CL_2)
  87
  88/* MGCOGE3NE */
  89#elif defined(CONFIG_MGCOGE3NE)
  90#define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max num of flash banks */
  91#define CONFIG_SYS_MAX_FLASH_SECT       1024    /*
  92                                                 * max num of sects on one
  93                                                 * chip
  94                                                 */
  95
  96#define CONFIG_SYS_FLASH_BASE_1 0x50000000
  97#define CONFIG_SYS_FLASH_SIZE_1 128
  98
  99#define CONFIG_SYS_FLASH_SIZE_2 0       /* dummy value to calc SYS_OR5 */
 100
 101#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \
 102                                        CONFIG_SYS_FLASH_BASE_1 }
 103
 104#define MTDIDS_DEFAULT          "nor2=app"
 105
 106/*
 107 * Bank 1 - 60x bus SDRAM
 108 * mgcoge3ne has 256MB
 109 * mgcoge2ne has 128MB
 110 */
 111#define SDRAM_MAX_SIZE 0x10000000                       /* max. 256 MB  */
 112#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT   (512 << 20)     /* less than 512 MB */
 113
 114#define CONFIG_SYS_OR1  ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & \
 115                           ORxS_SDAM_MSK)               |\
 116                        ORxS_BPD_4                      |\
 117                        ORxS_NUMR_13                    |\
 118                        ORxS_IBID)
 119
 120#define CONFIG_SYS_PSDMR (                              \
 121                        PSDMR_PBI                       |\
 122                        PSDMR_RFEN                      |\
 123                        PSDMR_BSMA_A13_A15              |\
 124                        PSDMR_RFRC_5_CLK                |\
 125                        PSDMR_PRETOACT_2W               |\
 126                        PSDMR_ACTTORW_2W                |\
 127                        PSDMR_LDOTOPRE_1C               |\
 128                        PSDMR_WRC_1C                    |\
 129                        PSDMR_CL_2)
 130
 131#define CONFIG_SYS_SDRAM_LIST   {                                       \
 132        {       .size   = 256 << 20,                                    \
 133                .or1    = ORxS_ROWST_PBI1_A4,                           \
 134                .psdmr  = PSDMR_SDAM_A17_IS_A5 | PSDMR_SDA10_PBI1_A6,   \
 135        },                                                              \
 136        {       .size   = 128 << 20,                                    \
 137                .or1    = ORxS_ROWST_PBI1_A5,                           \
 138                .psdmr  = PSDMR_SDAM_A16_IS_A5 | PSDMR_SDA10_PBI1_A7,   \
 139        },                                                              \
 140}
 141#endif /* defined(CONFIG_MGCOGE3NE) */
 142
 143/* include further common stuff for all keymile 82xx boards */
 144/*
 145 * Select serial console configuration
 146 *
 147 * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
 148 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
 149 * for SCC).
 150 */
 151#define CONFIG_CONS_ON_SMC              /* Console is on SMC         */
 152#undef  CONFIG_CONS_ON_SCC              /* It's not on SCC           */
 153#undef  CONFIG_CONS_NONE                /* It's not on external UART */
 154#define CONFIG_CONS_INDEX       2       /* SMC2 is used for console  */
 155#define CONFIG_SYS_SMC_RXBUFLEN 128
 156#define CONFIG_SYS_MAXIDLE      10
 157
 158/*
 159 * Select ethernet configuration
 160 *
 161 * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
 162 * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
 163 * SCC, 1-3 for FCC)
 164 *
 165 * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
 166 * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
 167 * must be unset.
 168 */
 169#define CONFIG_ETHER_ON_SCC             /* Ethernet is on SCC */
 170#undef  CONFIG_ETHER_ON_FCC             /* Ethernet is not on FCC     */
 171#undef  CONFIG_ETHER_NONE               /* No external Ethernet   */
 172
 173#define CONFIG_ETHER_INDEX      4
 174#define CONFIG_HAS_ETH0
 175#define CONFIG_SYS_SCC_TOUT_LOOP        10000000
 176
 177#define CONFIG_SYS_CMXSCR_VALUE (CMXSCR_RS4CS_CLK7 | CMXSCR_TS4CS_CLK8)
 178
 179#ifndef CONFIG_8260_CLKIN
 180#define CONFIG_8260_CLKIN       66000000        /* in Hz */
 181#endif
 182
 183#define BOOTFLASH_START         0xFE000000
 184
 185#define CONFIG_KM_CONSOLE_TTY   "ttyCPM0"
 186
 187#define MTDPARTS_DEFAULT        "mtdparts="                             \
 188        "app:"                                                          \
 189                "768k(u-boot),"                                         \
 190                "128k(env),"                                            \
 191                "128k(envred),"                                         \
 192                "3072k(free),"                                          \
 193                "-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ")"
 194
 195/*
 196 * Default environment settings
 197 */
 198#define CONFIG_EXTRA_ENV_SETTINGS                                       \
 199        CONFIG_KM_BOARD_EXTRA_ENV                                       \
 200        CONFIG_KM_DEF_ENV                                               \
 201        "unlock=yes\0"                                                  \
 202        "newenv="                                                       \
 203                "prot off 0xFE0C0000 +0x40000 && "                      \
 204                "era 0xFE0C0000 +0x40000\0"                             \
 205        "arch=ppc_82xx\0"                                       \
 206        ""
 207
 208#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 209
 210#define CONFIG_SYS_MONITOR_LEN          (768 << 10)
 211
 212#define CONFIG_ENV_IS_IN_FLASH
 213
 214#ifdef CONFIG_ENV_IS_IN_FLASH
 215#define CONFIG_ENV_SECT_SIZE    0x20000
 216#define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + \
 217                                        CONFIG_SYS_MONITOR_LEN)
 218#define CONFIG_ENV_OFFSET       CONFIG_SYS_MONITOR_LEN
 219
 220/* Address and size of Redundant Environment Sector     */
 221#define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET + \
 222                                                CONFIG_ENV_SECT_SIZE)
 223#define CONFIG_ENV_SIZE_REDUND          (CONFIG_ENV_SIZE)
 224#endif /* CONFIG_ENV_IS_IN_FLASH */
 225
 226/* enable I2C and select the hardware/software driver */
 227#define CONFIG_SYS_I2C
 228#define CONFIG_SYS_I2C_SOFT             /* I2C bit-banged */
 229#define CONFIG_SYS_I2C_INIT_BOARD
 230#define CONFIG_SYS_NUM_I2C_BUSES        3
 231#define CONFIG_SYS_I2C_MAX_HOPS         1
 232#define CONFIG_SYS_I2C_SOFT_SPEED       50000
 233#define CONFIG_SYS_I2C_SPEED            CONFIG_SYS_I2C_SOFT_SPEED
 234#define CONFIG_SYS_I2C_SOFT_SLAVE       0x7F
 235#define CONFIG_SYS_I2C_BUSES    {{0, {I2C_NULL_HOP} }, \
 236                        {0, {{I2C_MUX_PCA9542, 0x70, 0} } }, \
 237                        {0, {{I2C_MUX_PCA9542, 0x70, 1} } } }
 238
 239#define CONFIG_KM_IVM_BUS               1       /* I2C2 (Mux-Port 1)*/
 240#define CONFIG_KM_I2C_ABORT
 241
 242/*
 243 * Software (bit-bang) I2C driver configuration
 244 */
 245
 246#define I2C_PORT        3               /* Port A=0, B=1, C=2, D=3 */
 247#define I2C_ACTIVE      (iop->pdir |=  0x00010000)
 248#define I2C_TRISTATE    (iop->pdir &= ~0x00010000)
 249#define I2C_READ        ((iop->pdat & 0x00010000) != 0)
 250#define I2C_SDA(bit)    do { \
 251                                if (bit) \
 252                                        iop->pdat |=  0x00010000; \
 253                                else \
 254                                        iop->pdat &= ~0x00010000; \
 255                        } while (0)
 256#define I2C_SCL(bit)    do { \
 257                                if (bit) \
 258                                        iop->pdat |=  0x00020000; \
 259                                else \
 260                                        iop->pdat &= ~0x00020000; \
 261                        } while (0)
 262#define I2C_DELAY       udelay(5)       /* 1/4 I2C clock duration */
 263
 264#ifndef __ASSEMBLY__
 265void set_sda(int state);
 266void set_scl(int state);
 267int get_sda(void);
 268int get_scl(void);
 269#endif
 270
 271/* I2C SYSMON (LM75, AD7414 is almost compatible)                       */
 272#define CONFIG_DTT_LM75                 /* ON Semi's LM75               */
 273#define CONFIG_DTT_SENSORS      {0}     /* Sensor addresses             */
 274#define CONFIG_SYS_DTT_MAX_TEMP 70
 275#define CONFIG_SYS_DTT_HYSTERESIS       3
 276#define CONFIG_SYS_DTT_BUS_NUM          2
 277
 278#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 279
 280#define CONFIG_SYS_IMMR         0xF0000000
 281
 282#define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 283#define CONFIG_SYS_INIT_RAM_SIZE        0x2000 /* used size in DPRAM */
 284#define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 285                                                GENERATED_GBL_DATA_SIZE)
 286#define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 287
 288/* Hard reset configuration word */
 289#define CONFIG_SYS_HRCW_MASTER          0x0604b211
 290
 291/* No slaves */
 292#define CONFIG_SYS_HRCW_SLAVE1          0
 293#define CONFIG_SYS_HRCW_SLAVE2          0
 294#define CONFIG_SYS_HRCW_SLAVE3          0
 295#define CONFIG_SYS_HRCW_SLAVE4          0
 296#define CONFIG_SYS_HRCW_SLAVE5          0
 297#define CONFIG_SYS_HRCW_SLAVE6          0
 298#define CONFIG_SYS_HRCW_SLAVE7          0
 299
 300/* Initial Memory map for Linux */
 301#define CONFIG_SYS_BOOTMAPSZ            (8 << 20)
 302
 303#define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC8260 CPUs */
 304#if defined(CONFIG_CMD_KGDB)
 305#  define CONFIG_SYS_CACHELINE_SHIFT    5 /* log base 2 of the above value */
 306#endif
 307
 308#define CONFIG_SYS_HID0_INIT            0
 309#define CONFIG_SYS_HID0_FINAL           (HID0_ICE | HID0_IFEM | HID0_ABE)
 310
 311#define CONFIG_SYS_HID2         0
 312
 313#define CONFIG_SYS_SIUMCR               0x4020c200
 314#define CONFIG_SYS_SYPCR                0xFFFFFF83
 315#define CONFIG_SYS_BCR                  0x10000000
 316#define CONFIG_SYS_SCCR         (SCCR_PCI_MODE | SCCR_PCI_MODCK)
 317
 318/*
 319 *-----------------------------------------------------------------------
 320 * RMR - Reset Mode Register                                     5-5
 321 *-----------------------------------------------------------------------
 322 * turn on Checkstop Reset Enable
 323 */
 324#define CONFIG_SYS_RMR         0
 325
 326/*
 327 *-----------------------------------------------------------------------
 328 * TMCNTSC - Time Counter Status and Control                     4-40
 329 *-----------------------------------------------------------------------
 330 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 331 * and enable Time Counter
 332 */
 333#define CONFIG_SYS_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 334
 335/*
 336 *-----------------------------------------------------------------------
 337 * PISCR - Periodic Interrupt Status and Control                 4-42
 338 *-----------------------------------------------------------------------
 339 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 340 * Periodic timer
 341 */
 342#define CONFIG_SYS_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
 343
 344/*
 345 *-----------------------------------------------------------------------
 346 * RCCR - RISC Controller Configuration                         13-7
 347 *-----------------------------------------------------------------------
 348 */
 349#define CONFIG_SYS_RCCR        0
 350
 351/*
 352 * Init Memory Controller:
 353 *
 354 * Bank Bus     Machine PortSz  Device
 355 * ---- ---     ------- ------  ------
 356 *  0   60x     GPCM     8 bit  FLASH
 357 *  1   60x     SDRAM   32 bit  SDRAM
 358 *  3   60x     GPCM     8 bit  GPIO/PIGGY
 359 *  5   60x     GPCM    16 bit  CFG-Flash
 360 *
 361 */
 362/* Bank 0 - FLASH
 363 */
 364#define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)    |\
 365                         BRx_PS_8                       |\
 366                         BRx_MS_GPCM_P                  |\
 367                         BRx_V)
 368
 369#define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE)        |\
 370                         ORxG_CSNT                      |\
 371                         ORxG_ACS_DIV2                  |\
 372                         ORxG_SCY_5_CLK                 |\
 373                         ORxG_TRLX)
 374
 375#define CONFIG_SYS_MPTPR       0x1800
 376
 377/*
 378 *-----------------------------------------------------------------------------
 379 * Address for Mode Register Set (MRS) command
 380 *-----------------------------------------------------------------------------
 381 */
 382#define CONFIG_SYS_MRS_OFFS     0x00000110
 383#define CONFIG_SYS_PSRT        0x0e
 384
 385#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
 386                         BRx_PS_64              |\
 387                         BRx_MS_SDRAM_P         |\
 388                         BRx_V)
 389
 390#define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_OR1
 391
 392/*
 393 * UPIO FPGA (GPIO/PIGGY) on CS3 initialization values
 394 */
 395#define CONFIG_SYS_KMBEC_FPGA_BASE      0x30000000
 396#define CONFIG_SYS_KMBEC_FPGA_SIZE      128
 397
 398#define CONFIG_SYS_BR3_PRELIM   ((CONFIG_SYS_KMBEC_FPGA_BASE & BRx_BA_MSK) |\
 399                         BRx_PS_8 | BRx_MS_GPCM_P | BRx_V)
 400
 401#define CONFIG_SYS_OR3_PRELIM   (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) |\
 402                         ORxG_CSNT | ORxG_ACS_DIV2 |\
 403                         ORxG_SCY_3_CLK | ORxG_TRLX)
 404
 405/*
 406 * BFTICU board FPGA on CS4 initialization values
 407 */
 408#define CONFIG_SYS_FPGA_BASE    0x40000000
 409#define CONFIG_SYS_FPGA_SIZE    1 /*1KB*/
 410
 411#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_FPGA_BASE & BRx_BA_MSK) |\
 412                        BRx_PS_8 | BRx_MS_GPCM_P | BRx_V)
 413
 414#define CONFIG_SYS_OR4_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FPGA_SIZE << 10) |\
 415                         ORxG_CSNT | ORxG_ACS_DIV2 |\
 416                         ORxG_SCY_3_CLK | ORxG_TRLX)
 417
 418/*
 419 * CFG-Flash on CS5 initialization values
 420 */
 421#define CONFIG_SYS_BR5_PRELIM   ((CONFIG_SYS_FLASH_BASE_1 & BRx_BA_MSK) |\
 422                         BRx_PS_16 | BRx_MS_GPCM_P | BRx_V)
 423
 424#define CONFIG_SYS_OR5_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE_1 + \
 425                                 CONFIG_SYS_FLASH_SIZE_2) |\
 426                                 ORxG_CSNT | ORxG_ACS_DIV2 |\
 427                                 ORxG_SCY_5_CLK | ORxG_TRLX)
 428
 429#define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC     /* "bad" address */
 430
 431#define OF_TBCLK                (bd->bi_busfreq / 4)
 432#define OF_STDOUT_PATH          "/soc/cpm/serial@11a90"
 433
 434#endif /* __CONFIG_H */
 435