1/* 2 * Copyright 2016 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7#ifndef __CONFIG_H 8#define __CONFIG_H 9 10#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR 11 12#define CONFIG_SYS_FSL_CLK 13 14/* 15 * Size of malloc() pool 16 */ 17#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) 18 19#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR 20#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE 21 22/* XHCI Support - enabled by default */ 23#define CONFIG_HAS_FSL_XHCI_USB 24 25#ifdef CONFIG_HAS_FSL_XHCI_USB 26#define CONFIG_USB_XHCI_FSL 27#define CONFIG_USB_XHCI_DWC3 28#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 29#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 30#endif 31 32#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_XHCI_USB) 33#define CONFIG_USB_STORAGE 34#define CONFIG_CMD_EXT2 35#endif 36 37#define CONFIG_SYS_CLK_FREQ 100000000 38#define CONFIG_DDR_CLK_FREQ 100000000 39 40/* 41 * DDR: 800 MHz ( 1600 MT/s data rate ) 42 */ 43 44#define DDR_SDRAM_CFG 0x470c0008 45#define DDR_CS0_BNDS 0x008000bf 46#define DDR_CS0_CONFIG 0x80014302 47#define DDR_TIMING_CFG_0 0x50550004 48#define DDR_TIMING_CFG_1 0xbcb38c56 49#define DDR_TIMING_CFG_2 0x0040d120 50#define DDR_TIMING_CFG_3 0x010e1000 51#define DDR_TIMING_CFG_4 0x00000001 52#define DDR_TIMING_CFG_5 0x03401400 53#define DDR_SDRAM_CFG_2 0x00401010 54#define DDR_SDRAM_MODE 0x00061c60 55#define DDR_SDRAM_MODE_2 0x00180000 56#define DDR_SDRAM_INTERVAL 0x18600618 57#define DDR_DDR_WRLVL_CNTL 0x8655f605 58#define DDR_DDR_WRLVL_CNTL_2 0x05060607 59#define DDR_DDR_WRLVL_CNTL_3 0x05050505 60#define DDR_DDR_CDR1 0x80040000 61#define DDR_DDR_CDR2 0x00000001 62#define DDR_SDRAM_CLK_CNTL 0x02000000 63#define DDR_DDR_ZQ_CNTL 0x89080600 64#define DDR_CS0_CONFIG_2 0 65#define DDR_SDRAM_CFG_MEM_EN 0x80000000 66#define SDRAM_CFG2_D_INIT 0x00000010 67#define DDR_CDR2_VREF_TRAIN_EN 0x00000080 68#define SDRAM_CFG2_FRC_SR 0x80000000 69#define SDRAM_CFG_BI 0x00000001 70 71#ifdef CONFIG_RAMBOOT_PBL 72#define CONFIG_SYS_FSL_PBL_PBI \ 73 board/freescale/ls1021aiot/ls102xa_pbi.cfg 74#endif 75 76#ifdef CONFIG_SD_BOOT 77#define CONFIG_SYS_FSL_PBL_RCW \ 78 board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg 79#define CONFIG_SPL_FRAMEWORK 80#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" 81#define CONFIG_SPL_LIBCOMMON_SUPPORT 82#define CONFIG_SPL_LIBGENERIC_SUPPORT 83#define CONFIG_SPL_ENV_SUPPORT 84#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 85#define CONFIG_SPL_I2C_SUPPORT 86#define CONFIG_SPL_WATCHDOG_SUPPORT 87#define CONFIG_SPL_SERIAL_SUPPORT 88#define CONFIG_SPL_MMC_SUPPORT 89#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8 90 91#define CONFIG_SPL_TEXT_BASE 0x10000000 92#define CONFIG_SPL_MAX_SIZE 0x1a000 93#define CONFIG_SPL_STACK 0x1001d000 94#define CONFIG_SPL_PAD_TO 0x1c000 95#define CONFIG_SYS_TEXT_BASE 0x82000000 96 97#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ 98 CONFIG_SYS_MONITOR_LEN) 99#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 100#define CONFIG_SPL_BSS_START_ADDR 0x80100000 101#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 102#define CONFIG_SYS_MONITOR_LEN 0x80000 103#endif 104 105#ifdef CONFIG_QSPI_BOOT 106#define CONFIG_SYS_TEXT_BASE 0x40010000 107#endif 108 109#define CONFIG_NR_DRAM_BANKS 1 110 111#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 112#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 113 114/* 115 * Serial Port 116 */ 117#define CONFIG_CONS_INDEX 1 118#define CONFIG_SYS_NS16550_SERIAL 119#define CONFIG_SYS_NS16550_REG_SIZE 1 120#define CONFIG_SYS_NS16550_CLK get_serial_clock() 121 122/* 123 * I2C 124 */ 125#define CONFIG_CMD_I2C 126#define CONFIG_SYS_I2C 127#define CONFIG_SYS_I2C_MXC 128#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 129#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 130#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 131 132/* EEPROM */ 133#define CONFIG_ID_EEPROM 134#define CONFIG_SYS_I2C_EEPROM_NXID 135#define CONFIG_SYS_EEPROM_BUS_NUM 0 136#define CONFIG_SYS_I2C_EEPROM_ADDR 0x51 137#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 138 139/* 140 * MMC 141 */ 142#define CONFIG_CMD_MMC 143#define CONFIG_FSL_ESDHC 144 145/* SATA */ 146#define CONFIG_CMD_SCSI 147#define CONFIG_LIBATA 148#define CONFIG_SCSI_AHCI 149#define CONFIG_SCSI_AHCI_PLAT 150#ifndef PCI_DEVICE_ID_FREESCALE_AHCI 151#define PCI_DEVICE_ID_FREESCALE_AHCI 0x0440 152#endif 153#define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_FREESCALE, \ 154 PCI_DEVICE_ID_FREESCALE_AHCI} 155 156#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 157#define CONFIG_SYS_SCSI_MAX_LUN 1 158#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 159 CONFIG_SYS_SCSI_MAX_LUN) 160 161#define CONFIG_CMD_FAT 162 163/* SPI */ 164#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 165#define CONFIG_SPI_FLASH_SPANSION 166 167/* QSPI */ 168#define QSPI0_AMBA_BASE 0x40000000 169#define FSL_QSPI_FLASH_SIZE (1 << 24) 170#define FSL_QSPI_FLASH_NUM 2 171#define CONFIG_SPI_FLASH_BAR 172#define CONFIG_SPI_FLASH_SPANSION 173#endif 174 175/* DM SPI */ 176#if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) 177#define CONFIG_CMD_SF 178#define CONFIG_DM_SPI_FLASH 179#endif 180 181/* 182 * eTSEC 183 */ 184#define CONFIG_TSEC_ENET 185 186#ifdef CONFIG_TSEC_ENET 187#define CONFIG_MII 188#define CONFIG_MII_DEFAULT_TSEC 1 189#define CONFIG_TSEC1 1 190#define CONFIG_TSEC1_NAME "eTSEC1" 191#define CONFIG_TSEC2 1 192#define CONFIG_TSEC2_NAME "eTSEC2" 193 194#define TSEC1_PHY_ADDR 1 195#define TSEC2_PHY_ADDR 3 196 197#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 198#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 199 200#define TSEC1_PHYIDX 0 201#define TSEC2_PHYIDX 0 202 203#define CONFIG_ETHPRIME "eTSEC2" 204 205#define CONFIG_PHY_GIGE 206#define CONFIG_PHYLIB 207#define CONFIG_PHY_ATHEROS 208 209#define CONFIG_HAS_ETH0 210#define CONFIG_HAS_ETH1 211#define CONFIG_HAS_ETH2 212#endif 213 214/* PCIe */ 215#define CONFIG_PCIE1 /* PCIE controler 1 */ 216#define CONFIG_PCIE2 /* PCIE controler 2 */ 217 218#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" 219 220#ifdef CONFIG_PCI 221#define CONFIG_PCI_SCAN_SHOW 222#define CONFIG_CMD_PCI 223#endif 224 225#define CONFIG_CMD_PING 226#define CONFIG_CMD_DHCP 227#define CONFIG_CMD_MII 228 229#define CONFIG_CMDLINE_TAG 230#define CONFIG_CMDLINE_EDITING 231 232#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT) 233#undef CONFIG_CMD_IMLS 234#endif 235 236#define CONFIG_PEN_ADDR_BIG_ENDIAN 237#define CONFIG_LAYERSCAPE_NS_ACCESS 238#define CONFIG_SMP_PEN_ADDR 0x01ee0200 239#define COUNTER_FREQUENCY 12500000 240 241#define CONFIG_HWCONFIG 242#define HWCONFIG_BUFFER_SIZE 256 243 244#define CONFIG_FSL_DEVICE_DISABLE 245 246#define CONFIG_EXTRA_ENV_SETTINGS \ 247 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ 248"initrd_high=0xffffffff\0" \ 249"fdt_high=0xffffffff\0" 250 251/* 252 * Miscellaneous configurable options 253 */ 254#define CONFIG_SYS_LONGHELP /* undef to save memory */ 255#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 256#define CONFIG_AUTO_COMPLETE 257#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 258#define CONFIG_SYS_PBSIZE \ 259 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 260#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 261#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 262 263#define CONFIG_CMD_GREPENV 264#define CONFIG_CMD_MEMINFO 265 266#define CONFIG_SYS_LOAD_ADDR 0x82000000 267 268#define CONFIG_LS102XA_STREAM_ID 269 270#define CONFIG_SYS_INIT_SP_OFFSET \ 271 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 272#define CONFIG_SYS_INIT_SP_ADDR \ 273 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 274 275#ifdef CONFIG_SPL_BUILD 276#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 277#else 278/* start of monitor */ 279#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 280#endif 281 282#define CONFIG_SYS_QE_FW_ADDR 0x67f40000 283 284/* 285 * Environment 286 */ 287 288#define CONFIG_ENV_OVERWRITE 289 290#if defined(CONFIG_SD_BOOT) 291#define CONFIG_ENV_OFFSET 0x100000 292#define CONFIG_ENV_IS_IN_MMC 293#define CONFIG_SYS_MMC_ENV_DEV 0 294#define CONFIG_ENV_SIZE 0x2000 295#elif defined(CONFIG_QSPI_BOOT) 296#define CONFIG_ENV_IS_IN_SPI_FLASH 297#define CONFIG_ENV_SIZE 0x2000 298#define CONFIG_ENV_OFFSET 0x100000 299#define CONFIG_ENV_SECT_SIZE 0x10000 300#endif 301 302#define CONFIG_OF_BOARD_SETUP 303#define CONFIG_OF_STDOUT_VIA_ALIAS 304#define CONFIG_CMD_BOOTZ 305 306#define CONFIG_MISC_INIT_R 307 308/* Hash command with SHA acceleration supported in hardware */ 309 310#ifdef CONFIG_FSL_CAAM 311 312#define CONFIG_CMD_HASH 313 314#define CONFIG_SHA_HW_ACCEL 315 316#endif 317 318#include <asm/fsl_secure_boot.h> 319 320#endif 321