1/* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7#ifndef __CONFIG_H 8#define __CONFIG_H 9 10#define CONFIG_ARMV7_PSCI_1_0 11 12#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR 13 14#define CONFIG_SYS_FSL_CLK 15 16#define CONFIG_SKIP_LOWLEVEL_INIT 17#define CONFIG_DEEP_SLEEP 18 19/* 20 * Size of malloc() pool 21 */ 22#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) 23 24#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR 25#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE 26 27/* 28 * USB 29 */ 30 31/* 32 * EHCI Support - disbaled by default as 33 * there is no signal coming out of soc on 34 * this board for this controller. However, 35 * the silicon still has this controller, 36 * and anyone can use this controller by 37 * taking signals out on their board. 38 */ 39 40/*#define CONFIG_HAS_FSL_DR_USB*/ 41 42#ifdef CONFIG_HAS_FSL_DR_USB 43#define CONFIG_USB_EHCI 44#define CONFIG_USB_EHCI_FSL 45#define CONFIG_EHCI_HCD_INIT_AFTER_RESET 46#endif 47 48/* XHCI Support - enabled by default */ 49#define CONFIG_HAS_FSL_XHCI_USB 50 51#ifdef CONFIG_HAS_FSL_XHCI_USB 52#define CONFIG_USB_XHCI_FSL 53#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 54#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 55#endif 56 57#define CONFIG_SYS_CLK_FREQ 100000000 58#define CONFIG_DDR_CLK_FREQ 100000000 59 60#define DDR_SDRAM_CFG 0x470c0008 61#define DDR_CS0_BNDS 0x008000bf 62#define DDR_CS0_CONFIG 0x80014302 63#define DDR_TIMING_CFG_0 0x50550004 64#define DDR_TIMING_CFG_1 0xbcb38c56 65#define DDR_TIMING_CFG_2 0x0040d120 66#define DDR_TIMING_CFG_3 0x010e1000 67#define DDR_TIMING_CFG_4 0x00000001 68#define DDR_TIMING_CFG_5 0x03401400 69#define DDR_SDRAM_CFG_2 0x00401010 70#define DDR_SDRAM_MODE 0x00061c60 71#define DDR_SDRAM_MODE_2 0x00180000 72#define DDR_SDRAM_INTERVAL 0x18600618 73#define DDR_DDR_WRLVL_CNTL 0x8655f605 74#define DDR_DDR_WRLVL_CNTL_2 0x05060607 75#define DDR_DDR_WRLVL_CNTL_3 0x05050505 76#define DDR_DDR_CDR1 0x80040000 77#define DDR_DDR_CDR2 0x00000001 78#define DDR_SDRAM_CLK_CNTL 0x02000000 79#define DDR_DDR_ZQ_CNTL 0x89080600 80#define DDR_CS0_CONFIG_2 0 81#define DDR_SDRAM_CFG_MEM_EN 0x80000000 82#define SDRAM_CFG2_D_INIT 0x00000010 83#define DDR_CDR2_VREF_TRAIN_EN 0x00000080 84#define SDRAM_CFG2_FRC_SR 0x80000000 85#define SDRAM_CFG_BI 0x00000001 86 87#ifdef CONFIG_RAMBOOT_PBL 88#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021atwr/ls102xa_pbi.cfg 89#endif 90 91#ifdef CONFIG_SD_BOOT 92#ifdef CONFIG_SD_BOOT_QSPI 93#define CONFIG_SYS_FSL_PBL_RCW \ 94 board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg 95#else 96#define CONFIG_SYS_FSL_PBL_RCW \ 97 board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg 98#endif 99#define CONFIG_SPL_FRAMEWORK 100#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" 101 102#ifdef CONFIG_SECURE_BOOT 103/* 104 * HDR would be appended at end of image and copied to DDR along 105 * with U-Boot image. 106 */ 107#define CONFIG_U_BOOT_HDR_SIZE (16 << 10) 108#endif /* ifdef CONFIG_SECURE_BOOT */ 109 110#define CONFIG_SPL_TEXT_BASE 0x10000000 111#define CONFIG_SPL_MAX_SIZE 0x1a000 112#define CONFIG_SPL_STACK 0x1001d000 113#define CONFIG_SPL_PAD_TO 0x1c000 114#define CONFIG_SYS_TEXT_BASE 0x82000000 115 116#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ 117 CONFIG_SYS_MONITOR_LEN) 118#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 119#define CONFIG_SPL_BSS_START_ADDR 0x80100000 120#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 121 122#ifdef CONFIG_U_BOOT_HDR_SIZE 123/* 124 * HDR would be appended at end of image and copied to DDR along 125 * with U-Boot image. Here u-boot max. size is 512K. So if binary 126 * size increases then increase this size in case of secure boot as 127 * it uses raw u-boot image instead of fit image. 128 */ 129#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE) 130#else 131#define CONFIG_SYS_MONITOR_LEN 0x100000 132#endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */ 133#endif 134 135#ifdef CONFIG_QSPI_BOOT 136#define CONFIG_SYS_TEXT_BASE 0x40010000 137#endif 138 139#ifndef CONFIG_SYS_TEXT_BASE 140#define CONFIG_SYS_TEXT_BASE 0x60100000 141#endif 142 143#define CONFIG_NR_DRAM_BANKS 1 144#define PHYS_SDRAM 0x80000000 145#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) 146 147#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 148#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 149 150#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ 151 !defined(CONFIG_QSPI_BOOT) 152#define CONFIG_U_QE 153#endif 154 155/* 156 * IFC Definitions 157 */ 158#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 159#define CONFIG_FSL_IFC 160#define CONFIG_SYS_FLASH_BASE 0x60000000 161#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 162 163#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 164#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 165 CSPR_PORT_SIZE_16 | \ 166 CSPR_MSEL_NOR | \ 167 CSPR_V) 168#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 169 170/* NOR Flash Timing Params */ 171#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 172 CSOR_NOR_TRHZ_80) 173#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 174 FTIM0_NOR_TEADC(0x5) | \ 175 FTIM0_NOR_TAVDS(0x0) | \ 176 FTIM0_NOR_TEAHC(0x5)) 177#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 178 FTIM1_NOR_TRAD_NOR(0x1A) | \ 179 FTIM1_NOR_TSEQRAD_NOR(0x13)) 180#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 181 FTIM2_NOR_TCH(0x4) | \ 182 FTIM2_NOR_TWP(0x1c) | \ 183 FTIM2_NOR_TWPH(0x0e)) 184#define CONFIG_SYS_NOR_FTIM3 0 185 186#define CONFIG_FLASH_CFI_DRIVER 187#define CONFIG_SYS_FLASH_CFI 188#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 189#define CONFIG_SYS_FLASH_QUIET_TEST 190#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 191 192#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 193#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 194#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 195#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 196 197#define CONFIG_SYS_FLASH_EMPTY_INFO 198#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } 199 200#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 201#define CONFIG_SYS_WRITE_SWAPPED_DATA 202#endif 203 204/* CPLD */ 205 206#define CONFIG_SYS_CPLD_BASE 0x7fb00000 207#define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 208 209#define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 210#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ 211 CSPR_PORT_SIZE_8 | \ 212 CSPR_MSEL_GPCM | \ 213 CSPR_V) 214#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) 215#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 216 CSOR_NOR_NOR_MODE_AVD_NOR | \ 217 CSOR_NOR_TRHZ_80) 218 219/* CPLD Timing parameters for IFC GPCM */ 220#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \ 221 FTIM0_GPCM_TEADC(0xf) | \ 222 FTIM0_GPCM_TEAHC(0xf)) 223#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 224 FTIM1_GPCM_TRAD(0x3f)) 225#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 226 FTIM2_GPCM_TCH(0xf) | \ 227 FTIM2_GPCM_TWP(0xff)) 228#define CONFIG_SYS_FPGA_FTIM3 0x0 229#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 230#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 231#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 232#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 233#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 234#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 235#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 236#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 237#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT 238#define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR 239#define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK 240#define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR 241#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0 242#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1 243#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2 244#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3 245 246/* 247 * Serial Port 248 */ 249#ifdef CONFIG_LPUART 250#define CONFIG_LPUART_32B_REG 251#else 252#define CONFIG_CONS_INDEX 1 253#define CONFIG_SYS_NS16550_SERIAL 254#ifndef CONFIG_DM_SERIAL 255#define CONFIG_SYS_NS16550_REG_SIZE 1 256#endif 257#define CONFIG_SYS_NS16550_CLK get_serial_clock() 258#endif 259 260/* 261 * I2C 262 */ 263#define CONFIG_SYS_I2C 264#define CONFIG_SYS_I2C_MXC 265#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 266#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 267#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 268 269/* EEPROM */ 270#define CONFIG_ID_EEPROM 271#define CONFIG_SYS_I2C_EEPROM_NXID 272#define CONFIG_SYS_EEPROM_BUS_NUM 1 273#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 274#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 275#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 276#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 277 278/* 279 * MMC 280 */ 281#define CONFIG_FSL_ESDHC 282 283/* SPI */ 284#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 285/* QSPI */ 286#define QSPI0_AMBA_BASE 0x40000000 287#define FSL_QSPI_FLASH_SIZE (1 << 24) 288#define FSL_QSPI_FLASH_NUM 2 289 290/* DSPI */ 291#endif 292 293/* DM SPI */ 294#if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) 295#define CONFIG_DM_SPI_FLASH 296#endif 297 298/* 299 * Video 300 */ 301#ifdef CONFIG_VIDEO_FSL_DCU_FB 302#define CONFIG_VIDEO_LOGO 303#define CONFIG_VIDEO_BMP_LOGO 304 305#define CONFIG_FSL_DCU_SII9022A 306#define CONFIG_SYS_I2C_DVI_BUS_NUM 1 307#define CONFIG_SYS_I2C_DVI_ADDR 0x39 308#endif 309 310/* 311 * eTSEC 312 */ 313#define CONFIG_TSEC_ENET 314 315#ifdef CONFIG_TSEC_ENET 316#define CONFIG_MII 317#define CONFIG_MII_DEFAULT_TSEC 1 318#define CONFIG_TSEC1 1 319#define CONFIG_TSEC1_NAME "eTSEC1" 320#define CONFIG_TSEC2 1 321#define CONFIG_TSEC2_NAME "eTSEC2" 322#define CONFIG_TSEC3 1 323#define CONFIG_TSEC3_NAME "eTSEC3" 324 325#define TSEC1_PHY_ADDR 2 326#define TSEC2_PHY_ADDR 0 327#define TSEC3_PHY_ADDR 1 328 329#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 330#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 331#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 332 333#define TSEC1_PHYIDX 0 334#define TSEC2_PHYIDX 0 335#define TSEC3_PHYIDX 0 336 337#define CONFIG_ETHPRIME "eTSEC1" 338 339#define CONFIG_PHY_GIGE 340#define CONFIG_PHYLIB 341#define CONFIG_PHY_ATHEROS 342 343#define CONFIG_HAS_ETH0 344#define CONFIG_HAS_ETH1 345#define CONFIG_HAS_ETH2 346#endif 347 348/* PCIe */ 349#define CONFIG_PCIE1 /* PCIE controller 1 */ 350#define CONFIG_PCIE2 /* PCIE controller 2 */ 351 352#ifdef CONFIG_PCI 353#define CONFIG_PCI_SCAN_SHOW 354#define CONFIG_CMD_PCI 355#endif 356 357#define CONFIG_CMDLINE_TAG 358#define CONFIG_CMDLINE_EDITING 359 360#define CONFIG_PEN_ADDR_BIG_ENDIAN 361#define CONFIG_LAYERSCAPE_NS_ACCESS 362#define CONFIG_SMP_PEN_ADDR 0x01ee0200 363#define COUNTER_FREQUENCY 12500000 364 365#define CONFIG_HWCONFIG 366#define HWCONFIG_BUFFER_SIZE 256 367 368#define CONFIG_FSL_DEVICE_DISABLE 369 370 371#ifdef CONFIG_LPUART 372#define CONFIG_EXTRA_ENV_SETTINGS \ 373 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ 374 "initrd_high=0xffffffff\0" \ 375 "fdt_high=0xffffffff\0" 376#else 377#define CONFIG_EXTRA_ENV_SETTINGS \ 378 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ 379 "initrd_high=0xffffffff\0" \ 380 "fdt_high=0xffffffff\0" 381#endif 382 383/* 384 * Miscellaneous configurable options 385 */ 386#define CONFIG_SYS_LONGHELP /* undef to save memory */ 387#define CONFIG_AUTO_COMPLETE 388#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 389#define CONFIG_SYS_PBSIZE \ 390 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 391#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 392#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 393 394#define CONFIG_SYS_MEMTEST_START 0x80000000 395#define CONFIG_SYS_MEMTEST_END 0x9fffffff 396 397#define CONFIG_SYS_LOAD_ADDR 0x82000000 398 399#define CONFIG_LS102XA_STREAM_ID 400 401#define CONFIG_SYS_INIT_SP_OFFSET \ 402 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 403#define CONFIG_SYS_INIT_SP_ADDR \ 404 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 405 406#ifdef CONFIG_SPL_BUILD 407#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 408#else 409#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 410#endif 411 412#define CONFIG_SYS_QE_FW_ADDR 0x600c0000 413 414/* 415 * Environment 416 */ 417#define CONFIG_ENV_OVERWRITE 418 419#if defined(CONFIG_SD_BOOT) 420#define CONFIG_ENV_OFFSET 0x100000 421#define CONFIG_ENV_IS_IN_MMC 422#define CONFIG_SYS_MMC_ENV_DEV 0 423#define CONFIG_ENV_SIZE 0x20000 424#elif defined(CONFIG_QSPI_BOOT) 425#define CONFIG_ENV_IS_IN_SPI_FLASH 426#define CONFIG_ENV_SIZE 0x2000 427#define CONFIG_ENV_OFFSET 0x100000 428#define CONFIG_ENV_SECT_SIZE 0x10000 429#else 430#define CONFIG_ENV_IS_IN_FLASH 431#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 432#define CONFIG_ENV_SIZE 0x20000 433#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 434#endif 435 436#define CONFIG_MISC_INIT_R 437 438/* Hash command with SHA acceleration supported in hardware */ 439#ifdef CONFIG_FSL_CAAM 440#define CONFIG_CMD_HASH 441#define CONFIG_SHA_HW_ACCEL 442#endif 443 444#include <asm/fsl_secure_boot.h> 445#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 446 447#endif 448