1/* 2 * Copyright 2015 Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7#ifndef __LS1043ARDB_H__ 8#define __LS1043ARDB_H__ 9 10#include "ls1043a_common.h" 11 12#if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT) 13#define CONFIG_SYS_TEXT_BASE 0x82000000 14#else 15#define CONFIG_SYS_TEXT_BASE 0x60100000 16#endif 17 18#define CONFIG_SYS_CLK_FREQ 100000000 19#define CONFIG_DDR_CLK_FREQ 100000000 20 21#define CONFIG_LAYERSCAPE_NS_ACCESS 22#define CONFIG_MISC_INIT_R 23 24#define CONFIG_DIMM_SLOTS_PER_CTLR 1 25/* Physical Memory Map */ 26#define CONFIG_CHIP_SELECTS_PER_CTRL 4 27#define CONFIG_NR_DRAM_BANKS 2 28 29#define CONFIG_SYS_SPD_BUS_NUM 0 30 31#define CONFIG_FSL_DDR_BIST 32#ifndef CONFIG_SPL 33#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ 34#endif 35#define CONFIG_SYS_DDR_RAW_TIMING 36#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 37#define CONFIG_MEM_INIT_VALUE 0xdeadbeef 38 39#ifdef CONFIG_RAMBOOT_PBL 40#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043ardb/ls1043ardb_pbi.cfg 41#endif 42 43#ifdef CONFIG_NAND_BOOT 44#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg 45#endif 46 47#ifdef CONFIG_SD_BOOT 48#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg 49#endif 50 51/* 52 * NOR Flash Definitions 53 */ 54#define CONFIG_SYS_NOR_CSPR_EXT (0x0) 55#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 56#define CONFIG_SYS_NOR_CSPR \ 57 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 58 CSPR_PORT_SIZE_16 | \ 59 CSPR_MSEL_NOR | \ 60 CSPR_V) 61 62/* NOR Flash Timing Params */ 63#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 64 CSOR_NOR_TRHZ_80) 65#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ 66 FTIM0_NOR_TEADC(0x1) | \ 67 FTIM0_NOR_TAVDS(0x0) | \ 68 FTIM0_NOR_TEAHC(0xc)) 69#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1c) | \ 70 FTIM1_NOR_TRAD_NOR(0xb) | \ 71 FTIM1_NOR_TSEQRAD_NOR(0x9)) 72#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) | \ 73 FTIM2_NOR_TCH(0x4) | \ 74 FTIM2_NOR_TWPH(0x8) | \ 75 FTIM2_NOR_TWP(0x10)) 76#define CONFIG_SYS_NOR_FTIM3 0 77#define CONFIG_SYS_IFC_CCR 0x01000000 78 79#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 80#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 81#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 82#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 83 84#define CONFIG_SYS_FLASH_EMPTY_INFO 85#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } 86 87#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 88#define CONFIG_SYS_WRITE_SWAPPED_DATA 89 90/* 91 * NAND Flash Definitions 92 */ 93#ifndef SPL_NO_IFC 94#define CONFIG_NAND_FSL_IFC 95#endif 96 97#define CONFIG_SYS_NAND_BASE 0x7e800000 98#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 99 100#define CONFIG_SYS_NAND_CSPR_EXT (0x0) 101#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 102 | CSPR_PORT_SIZE_8 \ 103 | CSPR_MSEL_NAND \ 104 | CSPR_V) 105#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 106#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 107 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 108 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 109 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 110 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 111 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ 112 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ 113 114#define CONFIG_SYS_NAND_ONFI_DETECTION 115 116#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ 117 FTIM0_NAND_TWP(0x18) | \ 118 FTIM0_NAND_TWCHT(0x7) | \ 119 FTIM0_NAND_TWH(0xa)) 120#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 121 FTIM1_NAND_TWBE(0x39) | \ 122 FTIM1_NAND_TRR(0xe) | \ 123 FTIM1_NAND_TRP(0x18)) 124#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ 125 FTIM2_NAND_TREH(0xa) | \ 126 FTIM2_NAND_TWHRE(0x1e)) 127#define CONFIG_SYS_NAND_FTIM3 0x0 128 129#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 130#define CONFIG_SYS_MAX_NAND_DEVICE 1 131#define CONFIG_MTD_NAND_VERIFY_WRITE 132#define CONFIG_CMD_NAND 133 134#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 135 136#ifdef CONFIG_NAND_BOOT 137#define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */ 138#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO 139#define CONFIG_SYS_NAND_U_BOOT_SIZE (1024 << 10) 140#endif 141 142/* 143 * CPLD 144 */ 145#define CONFIG_SYS_CPLD_BASE 0x7fb00000 146#define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 147 148#define CONFIG_SYS_CPLD_CSPR_EXT (0x0) 149#define CONFIG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ 150 CSPR_PORT_SIZE_8 | \ 151 CSPR_MSEL_GPCM | \ 152 CSPR_V) 153#define CONFIG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024) 154#define CONFIG_SYS_CPLD_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 155 CSOR_NOR_NOR_MODE_AVD_NOR | \ 156 CSOR_NOR_TRHZ_80) 157 158/* CPLD Timing parameters for IFC GPCM */ 159#define CONFIG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \ 160 FTIM0_GPCM_TEADC(0xf) | \ 161 FTIM0_GPCM_TEAHC(0xf)) 162#define CONFIG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 163 FTIM1_GPCM_TRAD(0x3f)) 164#define CONFIG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 165 FTIM2_GPCM_TCH(0xf) | \ 166 FTIM2_GPCM_TWP(0xff)) 167#define CONFIG_SYS_CPLD_FTIM3 0x0 168 169/* IFC Timing Params */ 170#ifdef CONFIG_NAND_BOOT 171#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 172#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 173#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 174#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 175#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 176#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 177#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 178#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 179 180#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT 181#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 182#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 183#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 184#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 185#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 186#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 187#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 188#else 189#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT 190#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 191#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 192#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 193#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 194#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 195#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 196#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 197 198#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 199#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 200#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 201#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 202#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 203#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 204#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 205#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 206#endif 207 208#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_CPLD_CSPR_EXT 209#define CONFIG_SYS_CSPR2 CONFIG_SYS_CPLD_CSPR 210#define CONFIG_SYS_AMASK2 CONFIG_SYS_CPLD_AMASK 211#define CONFIG_SYS_CSOR2 CONFIG_SYS_CPLD_CSOR 212#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_CPLD_FTIM0 213#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_CPLD_FTIM1 214#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_CPLD_FTIM2 215#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3 216 217/* EEPROM */ 218#ifndef SPL_NO_EEPROM 219#define CONFIG_ID_EEPROM 220#define CONFIG_SYS_I2C_EEPROM_NXID 221#define CONFIG_SYS_EEPROM_BUS_NUM 0 222#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 223#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 224#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 225#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 226#endif 227 228/* 229 * Environment 230 */ 231#ifndef SPL_NO_ENV 232#define CONFIG_ENV_OVERWRITE 233#endif 234 235#if defined(CONFIG_NAND_BOOT) 236#define CONFIG_ENV_IS_IN_NAND 237#define CONFIG_ENV_SIZE 0x2000 238#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 239#elif defined(CONFIG_SD_BOOT) 240#define CONFIG_ENV_OFFSET (1024 * 1024) 241#define CONFIG_ENV_IS_IN_MMC 242#define CONFIG_SYS_MMC_ENV_DEV 0 243#define CONFIG_ENV_SIZE 0x2000 244#else 245#define CONFIG_ENV_IS_IN_FLASH 246#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000) 247#define CONFIG_ENV_SECT_SIZE 0x20000 248#define CONFIG_ENV_SIZE 0x20000 249#endif 250 251/* FMan */ 252#ifndef SPL_NO_FMAN 253#ifdef CONFIG_SYS_DPAA_FMAN 254#define CONFIG_FMAN_ENET 255#define CONFIG_PHYLIB 256#define CONFIG_PHYLIB_10G 257#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 258 259#define CONFIG_PHY_VITESSE 260#define CONFIG_PHY_REALTEK 261#define CONFIG_PHY_AQUANTIA 262#define AQR105_IRQ_MASK 0x40000000 263 264#define RGMII_PHY1_ADDR 0x1 265#define RGMII_PHY2_ADDR 0x2 266 267#define QSGMII_PORT1_PHY_ADDR 0x4 268#define QSGMII_PORT2_PHY_ADDR 0x5 269#define QSGMII_PORT3_PHY_ADDR 0x6 270#define QSGMII_PORT4_PHY_ADDR 0x7 271 272#define FM1_10GEC1_PHY_ADDR 0x1 273 274#define CONFIG_ETHPRIME "FM1@DTSEC3" 275#endif 276#endif 277 278/* QE */ 279#ifndef SPL_NO_QE 280#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ 281 !defined(CONFIG_QSPI_BOOT) 282#define CONFIG_U_QE 283#endif 284#define CONFIG_SYS_QE_FW_ADDR 0x60600000 285#endif 286 287/* USB */ 288#ifndef SPL_NO_USB 289#define CONFIG_HAS_FSL_XHCI_USB 290#ifdef CONFIG_HAS_FSL_XHCI_USB 291#define CONFIG_USB_XHCI_FSL 292#define CONFIG_USB_MAX_CONTROLLER_COUNT 3 293#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 294#endif 295#endif 296 297/* SATA */ 298#ifndef SPL_NO_SATA 299#define CONFIG_LIBATA 300#define CONFIG_SCSI_AHCI 301#define CONFIG_CMD_SCSI 302#ifndef CONFIG_CMD_FAT 303#define CONFIG_CMD_FAT 304#endif 305#ifndef CONFIG_CMD_EXT2 306#define CONFIG_CMD_EXT2 307#endif 308#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2 309#define CONFIG_SYS_SCSI_MAX_LUN 2 310#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 311 CONFIG_SYS_SCSI_MAX_LUN) 312#define SCSI_VEND_ID 0x1b4b 313#define SCSI_DEV_ID 0x9170 314#define CONFIG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID} 315#endif 316 317#include <asm/fsl_secure_boot.h> 318 319#endif /* __LS1043ARDB_H__ */ 320