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6
7#ifndef __LS1046AQDS_H__
8#define __LS1046AQDS_H__
9
10#include "ls1046a_common.h"
11
12#if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT)
13#define CONFIG_SYS_TEXT_BASE 0x82000000
14#elif defined(CONFIG_QSPI_BOOT)
15#define CONFIG_SYS_TEXT_BASE 0x40010000
16#else
17#define CONFIG_SYS_TEXT_BASE 0x60100000
18#endif
19
20#ifndef __ASSEMBLY__
21unsigned long get_board_sys_clk(void);
22unsigned long get_board_ddr_clk(void);
23#endif
24
25#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
26#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
27
28#define CONFIG_SKIP_LOWLEVEL_INIT
29
30#define CONFIG_LAYERSCAPE_NS_ACCESS
31
32#define CONFIG_DIMM_SLOTS_PER_CTLR 1
33
34#define CONFIG_CHIP_SELECTS_PER_CTRL 4
35#define CONFIG_NR_DRAM_BANKS 2
36
37#define CONFIG_DDR_SPD
38#define SPD_EEPROM_ADDRESS 0x51
39#define CONFIG_SYS_SPD_BUS_NUM 0
40
41#ifndef CONFIG_SPL
42#define CONFIG_FSL_DDR_INTERACTIVE
43#endif
44
45#define CONFIG_DDR_ECC
46#ifdef CONFIG_DDR_ECC
47#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
48#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
49#endif
50
51
52#ifdef CONFIG_FSL_DSPI
53#define CONFIG_SPI_FLASH_STMICRO
54#define CONFIG_SPI_FLASH_SST
55#define CONFIG_SPI_FLASH_EON
56#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
57#define CONFIG_SF_DEFAULT_BUS 1
58#define CONFIG_SF_DEFAULT_CS 0
59#endif
60#endif
61
62
63#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
64#ifdef CONFIG_FSL_QSPI
65#define CONFIG_SPI_FLASH_SPANSION
66#define FSL_QSPI_FLASH_SIZE (1 << 24)
67#define FSL_QSPI_FLASH_NUM 2
68#endif
69#endif
70
71#ifdef CONFIG_SYS_DPAA_FMAN
72#define CONFIG_FMAN_ENET
73#define CONFIG_PHYLIB
74#define CONFIG_PHY_VITESSE
75#define CONFIG_PHY_REALTEK
76#define CONFIG_PHYLIB_10G
77#define RGMII_PHY1_ADDR 0x1
78#define RGMII_PHY2_ADDR 0x2
79#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
80#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
81#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
82#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
83
84#define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
85#define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
86#define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
87#define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
88#endif
89
90#ifdef CONFIG_RAMBOOT_PBL
91#define CONFIG_SYS_FSL_PBL_PBI \
92 board/freescale/ls1046aqds/ls1046aqds_pbi.cfg
93#endif
94
95#ifdef CONFIG_NAND_BOOT
96#define CONFIG_SYS_FSL_PBL_RCW \
97 board/freescale/ls1046aqds/ls1046aqds_rcw_nand.cfg
98#endif
99
100#ifdef CONFIG_SD_BOOT
101#ifdef CONFIG_SD_BOOT_QSPI
102#define CONFIG_SYS_FSL_PBL_RCW \
103 board/freescale/ls1046aqds/ls1046aqds_rcw_sd_qspi.cfg
104#else
105#define CONFIG_SYS_FSL_PBL_RCW \
106 board/freescale/ls1046aqds/ls1046aqds_rcw_sd_ifc.cfg
107#endif
108#endif
109
110
111#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
112#define CONFIG_FSL_IFC
113
114
115
116
117
118
119#define CONFIG_SYS_FLASH_BASE 0x60000000
120#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
121#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
122
123#ifdef CONFIG_MTD_NOR_FLASH
124#define CONFIG_FLASH_CFI_DRIVER
125#define CONFIG_SYS_FLASH_CFI
126#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
127#define CONFIG_SYS_FLASH_QUIET_TEST
128#define CONFIG_FLASH_SHOW_PROGRESS 45
129#endif
130#endif
131
132
133#ifdef CONFIG_LPUART
134#define CONFIG_LPUART_32B_REG
135#define CFG_UART_MUX_MASK 0x6
136#define CFG_UART_MUX_SHIFT 1
137#define CFG_LPUART_EN 0x2
138#endif
139
140
141#define CONFIG_HAS_FSL_XHCI_USB
142#ifdef CONFIG_HAS_FSL_XHCI_USB
143#define CONFIG_USB_XHCI_HCD
144#define CONFIG_USB_XHCI_FSL
145#define CONFIG_USB_XHCI_DWC3
146#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
147#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
148#define CONFIG_CMD_USB
149#define CONFIG_USB_STORAGE
150#endif
151
152
153#define CONFIG_LIBATA
154#define CONFIG_SCSI_AHCI
155#define CONFIG_SCSI_AHCI_PLAT
156#define CONFIG_SCSI
157
158
159#define CONFIG_ID_EEPROM
160#define CONFIG_SYS_I2C_EEPROM_NXID
161#define CONFIG_SYS_EEPROM_BUS_NUM 0
162#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
163#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
164#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
165#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
166
167#define CONFIG_SYS_SATA AHCI_BASE_ADDR
168
169#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
170#define CONFIG_SYS_SCSI_MAX_LUN 1
171#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
172 CONFIG_SYS_SCSI_MAX_LUN)
173
174
175
176
177#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
178#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
179#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
180 CSPR_PORT_SIZE_16 | \
181 CSPR_MSEL_NOR | \
182 CSPR_V)
183#define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
184#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
185 + 0x8000000) | \
186 CSPR_PORT_SIZE_16 | \
187 CSPR_MSEL_NOR | \
188 CSPR_V)
189#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
190
191#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
192 CSOR_NOR_TRHZ_80)
193#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
194 FTIM0_NOR_TEADC(0x5) | \
195 FTIM0_NOR_TEAHC(0x5))
196#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
197 FTIM1_NOR_TRAD_NOR(0x1a) | \
198 FTIM1_NOR_TSEQRAD_NOR(0x13))
199#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
200 FTIM2_NOR_TCH(0x4) | \
201 FTIM2_NOR_TWPH(0xe) | \
202 FTIM2_NOR_TWP(0x1c))
203#define CONFIG_SYS_NOR_FTIM3 0
204
205#define CONFIG_SYS_MAX_FLASH_BANKS 2
206#define CONFIG_SYS_MAX_FLASH_SECT 1024
207#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
208#define CONFIG_SYS_FLASH_WRITE_TOUT 500
209
210#define CONFIG_SYS_FLASH_EMPTY_INFO
211#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
212 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
213
214#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
215#define CONFIG_SYS_WRITE_SWAPPED_DATA
216
217
218
219
220#define CONFIG_NAND_FSL_IFC
221
222#define CONFIG_SYS_NAND_BASE 0x7e800000
223#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
224
225#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
226
227#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
228 | CSPR_PORT_SIZE_8 \
229 | CSPR_MSEL_NAND \
230 | CSPR_V)
231#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
232#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN \
233 | CSOR_NAND_ECC_DEC_EN \
234 | CSOR_NAND_ECC_MODE_8 \
235 | CSOR_NAND_RAL_3 \
236 | CSOR_NAND_PGS_4K \
237 | CSOR_NAND_SPRZ_224 \
238 | CSOR_NAND_PB(64))
239
240#define CONFIG_SYS_NAND_ONFI_DETECTION
241
242#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
243 FTIM0_NAND_TWP(0x18) | \
244 FTIM0_NAND_TWCHT(0x7) | \
245 FTIM0_NAND_TWH(0xa))
246#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
247 FTIM1_NAND_TWBE(0x39) | \
248 FTIM1_NAND_TRR(0xe) | \
249 FTIM1_NAND_TRP(0x18))
250#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
251 FTIM2_NAND_TREH(0xa) | \
252 FTIM2_NAND_TWHRE(0x1e))
253#define CONFIG_SYS_NAND_FTIM3 0x0
254
255#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
256#define CONFIG_SYS_MAX_NAND_DEVICE 1
257#define CONFIG_MTD_NAND_VERIFY_WRITE
258#define CONFIG_CMD_NAND
259
260#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024)
261#endif
262
263#ifdef CONFIG_NAND_BOOT
264#define CONFIG_SPL_PAD_TO 0x40000
265#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
266#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
267#endif
268
269#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
270#define CONFIG_QIXIS_I2C_ACCESS
271#define CONFIG_SYS_I2C_EARLY_INIT
272#endif
273
274
275
276
277#define CONFIG_FSL_QIXIS
278
279#ifdef CONFIG_FSL_QIXIS
280#define QIXIS_BASE 0x7fb00000
281#define QIXIS_BASE_PHYS QIXIS_BASE
282#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
283#define QIXIS_LBMAP_SWITCH 6
284#define QIXIS_LBMAP_MASK 0x0f
285#define QIXIS_LBMAP_SHIFT 0
286#define QIXIS_LBMAP_DFLTBANK 0x00
287#define QIXIS_LBMAP_ALTBANK 0x04
288#define QIXIS_LBMAP_NAND 0x09
289#define QIXIS_LBMAP_SD 0x00
290#define QIXIS_LBMAP_SD_QSPI 0xff
291#define QIXIS_LBMAP_QSPI 0xff
292#define QIXIS_RCW_SRC_NAND 0x110
293#define QIXIS_RCW_SRC_SD 0x040
294#define QIXIS_RCW_SRC_QSPI 0x045
295#define QIXIS_RST_CTL_RESET 0x41
296#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
297#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
298#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
299
300#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
301#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
302 CSPR_PORT_SIZE_8 | \
303 CSPR_MSEL_GPCM | \
304 CSPR_V)
305#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
306#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
307 CSOR_NOR_NOR_MODE_AVD_NOR | \
308 CSOR_NOR_TRHZ_80)
309
310
311
312
313#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \
314 FTIM0_GPCM_TEADC(0x20) | \
315 FTIM0_GPCM_TEAHC(0x10))
316#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \
317 FTIM1_GPCM_TRAD(0x1f))
318#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \
319 FTIM2_GPCM_TCH(0x8) | \
320 FTIM2_GPCM_TWP(0xf0))
321#define CONFIG_SYS_FPGA_FTIM3 0x0
322#endif
323
324#ifdef CONFIG_NAND_BOOT
325#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
326#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
327#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
328#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
329#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
330#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
331#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
332#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
333#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
334#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
335#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
336#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
337#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
338#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
339#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
340#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
341#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
342#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
343#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
344#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
345#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
346#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
347#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
348#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
349#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
350#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
351#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
352#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
353#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
354#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
355#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
356#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
357#else
358#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
359#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
360#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
361#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
362#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
363#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
364#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
365#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
366#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
367#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
368#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
369#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
370#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
371#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
372#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
373#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
374#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
375#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
376#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
377#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
378#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
379#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
380#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
381#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
382#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
383#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
384#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
385#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
386#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
387#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
388#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
389#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
390#endif
391
392
393
394
395#define I2C_MUX_PCA_ADDR_PRI 0x77
396#define I2C_MUX_PCA_ADDR_SEC 0x76
397#define I2C_RETIMER_ADDR 0x18
398#define I2C_MUX_CH_DEFAULT 0x8
399#define I2C_MUX_CH_CH7301 0xC
400#define I2C_MUX_CH5 0xD
401#define I2C_MUX_CH6 0xE
402#define I2C_MUX_CH7 0xF
403
404#define I2C_MUX_CH_VOL_MONITOR 0xa
405
406
407#define I2C_VOL_MONITOR_ADDR 0x40
408#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
409#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
410#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
411
412#define CONFIG_VID_FLS_ENV "ls1046aqds_vdd_mv"
413#ifndef CONFIG_SPL_BUILD
414#define CONFIG_VID
415#endif
416#define CONFIG_VOL_MONITOR_IR36021_SET
417#define CONFIG_VOL_MONITOR_INA220
418
419#define VDD_MV_MIN 819
420#define VDD_MV_MAX 1212
421
422
423
424
425#define CONFIG_MISC_INIT_R
426#define CONFIG_SYS_LONGHELP
427#define CONFIG_AUTO_COMPLETE
428#define CONFIG_SYS_PBSIZE \
429 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
430#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
431
432#define CONFIG_SYS_MEMTEST_START 0x80000000
433#define CONFIG_SYS_MEMTEST_END 0x9fffffff
434
435#define CONFIG_SYS_HZ 1000
436
437#define CONFIG_SYS_INIT_SP_OFFSET \
438 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
439
440#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
441
442
443
444
445#define CONFIG_ENV_OVERWRITE
446
447#ifdef CONFIG_NAND_BOOT
448#define CONFIG_ENV_IS_IN_NAND
449#define CONFIG_ENV_SIZE 0x2000
450#define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
451#elif defined(CONFIG_SD_BOOT)
452#define CONFIG_ENV_OFFSET (1024 * 1024)
453#define CONFIG_ENV_IS_IN_MMC
454#define CONFIG_SYS_MMC_ENV_DEV 0
455#define CONFIG_ENV_SIZE 0x2000
456#elif defined(CONFIG_QSPI_BOOT)
457#define CONFIG_ENV_IS_IN_SPI_FLASH
458#define CONFIG_ENV_SIZE 0x2000
459#define CONFIG_ENV_OFFSET 0x100000
460#define CONFIG_ENV_SECT_SIZE 0x10000
461#else
462#define CONFIG_ENV_IS_IN_FLASH
463#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000)
464#define CONFIG_ENV_SECT_SIZE 0x20000
465#define CONFIG_ENV_SIZE 0x20000
466#endif
467
468#define CONFIG_CMDLINE_TAG
469
470#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
471#define CONFIG_BOOTCOMMAND "sf probe && sf read $kernel_load " \
472 "e0000 f00000 && bootm $kernel_load"
473#else
474#define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \
475 "$kernel_size && bootm $kernel_load"
476#endif
477
478#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
479#define MTDPARTS_DEFAULT "mtdparts=1550000.quadspi:2m(uboot)," \
480 "14m(free)"
481#else
482#define MTDPARTS_DEFAULT "mtdparts=60000000.nor:" \
483 "2m@0x100000(nor_bank0_uboot),"\
484 "40m@0x1100000(nor_bank0_fit)," \
485 "7m(nor_bank0_user)," \
486 "2m@0x4100000(nor_bank4_uboot)," \
487 "40m@0x5100000(nor_bank4_fit),"\
488 "-(nor_bank4_user);" \
489 "7e800000.flash:" \
490 "4m(nand_uboot),36m(nand_kernel)," \
491 "472m(nand_free);spi0.0:2m(uboot)," \
492 "14m(free)"
493#endif
494
495#include <asm/fsl_secure_boot.h>
496
497#endif
498
