LXR uboot/include/configs/lwmon5.h

   1/*
   2 * (C) Copyright 2007-2013
   3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4 *
   5 * SPDX-License-Identifier:     GPL-2.0+
   6 */
   7
   8/*
   9 * lwmon5.h - configuration for lwmon5 board
  10 */
  11#ifndef __CONFIG_H
  12#define __CONFIG_H
  13
  14/*
  15 * High Level Configuration Options
  16 */
  17#define CONFIG_LWMON5           1               /* Board is lwmon5      */
  18#define CONFIG_440EPX           1               /* Specific PPC440EPx   */
  19#define CONFIG_440              1               /* ... PPC440 family    */
  20
  21#define CONFIG_SYS_TEXT_BASE    0xFFF80000
  22#define CONFIG_HOSTNAME         lwmon5
  23
  24#define CONFIG_SYS_CLK_FREQ     33300000        /* external freq to pll */
  25
  26#define CONFIG_4xx_DCACHE               /* enable cache in SDRAM        */
  27
  28#define CONFIG_BOARD_EARLY_INIT_R       /* Call board_early_init_r      */
  29#define CONFIG_BOARD_POSTCLK_INIT       /* Call board_postclk_init      */
  30#define CONFIG_MISC_INIT_R              /* Call misc_init_r             */
  31#define CONFIG_BOARD_RESET              /* Call board_reset             */
  32
  33/*
  34 * Base addresses -- Note these are effective addresses where the
  35 * actual resources get mapped (not physical addresses)
  36 */
  37#define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE    /* Start of U-Boot      */
  38#define CONFIG_SYS_MONITOR_LEN          0x80000
  39#define CONFIG_SYS_MALLOC_LEN           (1 << 20)       /* Reserved for malloc  */
  40
  41#define CONFIG_SYS_BOOT_BASE_ADDR       0xf0000000
  42#define CONFIG_SYS_SDRAM_BASE           0x00000000      /* _must_ be 0          */
  43#define CONFIG_SYS_FLASH_BASE           0xf8000000      /* start of FLASH       */
  44#define CONFIG_SYS_LIME_BASE_0          0xc0000000
  45#define CONFIG_SYS_LIME_BASE_1          0xc1000000
  46#define CONFIG_SYS_LIME_BASE_2          0xc2000000
  47#define CONFIG_SYS_LIME_BASE_3          0xc3000000
  48#define CONFIG_SYS_FPGA_BASE_0          0xc4000000
  49#define CONFIG_SYS_FPGA_BASE_1          0xc4200000
  50#define CONFIG_SYS_OCM_BASE             0xe0010000      /* ocm                  */
  51#define CONFIG_SYS_PCI_BASE             0xe0000000      /* Internal PCI regs    */
  52#define CONFIG_SYS_PCI_MEMBASE          0x80000000      /* mapped pci memory    */
  53#define CONFIG_SYS_PCI_MEMBASE1         (CONFIG_SYS_PCI_MEMBASE  + 0x10000000)
  54#define CONFIG_SYS_PCI_MEMBASE2         (CONFIG_SYS_PCI_MEMBASE1 + 0x10000000)
  55#define CONFIG_SYS_PCI_MEMBASE3         (CONFIG_SYS_PCI_MEMBASE2 + 0x10000000)
  56
  57#define CONFIG_SYS_USB2D0_BASE          0xe0000100
  58#define CONFIG_SYS_USB_DEVICE           0xe0000000
  59#define CONFIG_SYS_USB_HOST             0xe0000400
  60
  61/*
  62 * Initial RAM & stack pointer
  63 *
  64 * On LWMON5 we use D-cache as init-ram and stack pointer. We also move
  65 * the POST_WORD from OCM to a 440EPx register that preserves it's
  66 * content during reset (GPT0_COMP6). This way we reserve the OCM (16k)
  67 * for logbuffer only. (GPT0_COMP1-COMP5 are reserved for logbuffer header.)
  68 */
  69#define CONFIG_SYS_INIT_RAM_DCACHE      1               /* d-cache as init ram  */
  70#define CONFIG_SYS_INIT_RAM_ADDR        0x70000000              /* DCache       */
  71#define CONFIG_SYS_INIT_RAM_SIZE                (4 << 10)
  72#define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
  73                                         GENERATED_GBL_DATA_SIZE)
  74#define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
  75
  76/* unused GPT0 COMP reg */
  77#define CONFIG_SYS_POST_WORD_ADDR       (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6)
  78#define CONFIG_SYS_OCM_SIZE             (16 << 10)
  79/* 440EPx errata CHIP 11: don't use last 4kbytes */
  80#define CONFIG_SYS_MEM_TOP_HIDE         (4 << 10)
  81
  82/* Additional registers for watchdog timer post test */
  83#define CONFIG_SYS_WATCHDOG_TIME_ADDR   (CONFIG_SYS_PERIPHERAL_BASE + GPT0_MASK2)
  84#define CONFIG_SYS_WATCHDOG_FLAGS_ADDR  (CONFIG_SYS_PERIPHERAL_BASE + GPT0_MASK1)
  85#define CONFIG_SYS_DSPIC_TEST_ADDR      CONFIG_SYS_WATCHDOG_FLAGS_ADDR
  86#define CONFIG_SYS_OCM_STATUS_ADDR      CONFIG_SYS_WATCHDOG_FLAGS_ADDR
  87#define CONFIG_SYS_WATCHDOG_MAGIC       0x12480000
  88#define CONFIG_SYS_WATCHDOG_MAGIC_MASK  0xFFFF0000
  89#define CONFIG_SYS_DSPIC_TEST_MASK      0x00000001
  90#define CONFIG_SYS_OCM_STATUS_OK        0x00009A00
  91#define CONFIG_SYS_OCM_STATUS_FAIL      0x0000A300
  92#define CONFIG_SYS_OCM_STATUS_MASK      0x0000FF00
  93
  94/*
  95 * Serial Port
  96 */
  97#define CONFIG_CONS_INDEX       2       /* Use UART1                    */
  98#define CONFIG_SYS_NS16550_SERIAL
  99#define CONFIG_SYS_NS16550_REG_SIZE     1
 100#define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 101#undef CONFIG_SYS_EXT_SERIAL_CLOCK              /* no external clock provided   */
 102
 103#define CONFIG_SYS_BAUDRATE_TABLE                                               \
 104        {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 105
 106/*
 107 * Environment
 108 */
 109#define CONFIG_ENV_IS_IN_FLASH          /* use FLASH for environment vars       */
 110
 111/*
 112 * FLASH related
 113 */
 114#define CONFIG_SYS_FLASH_CFI                    /* The flash is CFI compatible  */
 115#define CONFIG_FLASH_CFI_DRIVER                 /* Use common CFI driver        */
 116
 117#define CONFIG_SYS_FLASH0               0xFC000000
 118#define CONFIG_SYS_FLASH1               0xF8000000
 119#define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
 120
 121#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2     /* max number of memory banks           */
 122#define CONFIG_SYS_MAX_FLASH_SECT       512     /* max number of sectors on one chip    */
 123
 124#define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 125#define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 126
 127#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       /* use buffered writes (20x faster)     */
 128#define CONFIG_SYS_FLASH_PROTECTION             /* use hardware flash protection        */
 129
 130#define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
 131#define CONFIG_SYS_FLASH_QUIET_TEST             /* don't warn upon unknown flash        */
 132
 133#define CONFIG_ENV_SECT_SIZE    0x40000 /* size of one complete sector          */
 134#define CONFIG_ENV_ADDR         ((-CONFIG_SYS_MONITOR_LEN) - CONFIG_ENV_SECT_SIZE)
 135#define CONFIG_ENV_SIZE         0x2000  /* Total Size of Environment Sector     */
 136
 137/* Address and size of Redundant Environment Sector     */
 138#define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
 139#define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 140
 141/*
 142 * DDR SDRAM
 143 */
 144#define CONFIG_SYS_MBYTES_SDRAM         256
 145#define CONFIG_SYS_DDR_CACHED_ADDR      0x40000000      /* setup 2nd TLB cached here    */
 146#define CONFIG_DDR_DATA_EYE                     /* use DDR2 optimization        */
 147#define CONFIG_DDR_ECC                          /* enable ECC                   */
 148
 149/* POST support */
 150#define CONFIG_POST             (CONFIG_SYS_POST_CACHE          | \
 151                                 CONFIG_SYS_POST_CPU            | \
 152                                 CONFIG_SYS_POST_ECC            | \
 153                                 CONFIG_SYS_POST_ETHER          | \
 154                                 CONFIG_SYS_POST_FPU            | \
 155                                 CONFIG_SYS_POST_I2C            | \
 156                                 CONFIG_SYS_POST_MEMORY         | \
 157                                 CONFIG_SYS_POST_OCM            | \
 158                                 CONFIG_SYS_POST_RTC            | \
 159                                 CONFIG_SYS_POST_SPR            | \
 160                                 CONFIG_SYS_POST_UART           | \
 161                                 CONFIG_SYS_POST_SYSMON         | \
 162                                 CONFIG_SYS_POST_WATCHDOG       | \
 163                                 CONFIG_SYS_POST_DSP            | \
 164                                 CONFIG_SYS_POST_BSPEC1         | \
 165                                 CONFIG_SYS_POST_BSPEC2         | \
 166                                 CONFIG_SYS_POST_BSPEC3         | \
 167                                 CONFIG_SYS_POST_BSPEC4         | \
 168                                 CONFIG_SYS_POST_BSPEC5)
 169
 170/* Define here the base-addresses of the UARTs to test in POST */
 171#define CONFIG_SYS_POST_UART_TABLE      { CONFIG_SYS_NS16550_COM1, \
 172                        CONFIG_SYS_NS16550_COM2 }
 173
 174#define CONFIG_POST_UART  {                             \
 175        "UART test",                                    \
 176        "uart",                                         \
 177        "This test verifies the UART operation.",       \
 178        POST_RAM | POST_SLOWTEST | POST_ALWAYS | POST_MANUAL,   \
 179        &uart_post_test,                                \
 180        NULL,                                           \
 181        NULL,                                           \
 182        CONFIG_SYS_POST_UART                            \
 183        }
 184
 185#define CONFIG_POST_WATCHDOG  {                         \
 186        "Watchdog timer test",                          \
 187        "watchdog",                                     \
 188        "This test checks the watchdog timer.",         \
 189        POST_RAM | POST_POWERON | POST_SLOWTEST | POST_MANUAL | POST_REBOOT, \
 190        &lwmon5_watchdog_post_test,                     \
 191        NULL,                                           \
 192        NULL,                                           \
 193        CONFIG_SYS_POST_WATCHDOG                        \
 194        }
 195
 196#define CONFIG_POST_BSPEC1    {                         \
 197        "dsPIC init test",                              \
 198        "dspic_init",                                   \
 199        "This test returns result of dsPIC READY test run earlier.",    \
 200        POST_RAM | POST_ALWAYS,                         \
 201        &dspic_init_post_test,                          \
 202        NULL,                                           \
 203        NULL,                                           \
 204        CONFIG_SYS_POST_BSPEC1                          \
 205        }
 206
 207#define CONFIG_POST_BSPEC2    {                         \
 208        "dsPIC test",                                   \
 209        "dspic",                                        \
 210        "This test gets result of dsPIC POST and dsPIC version.",       \
 211        POST_RAM | POST_ALWAYS,                         \
 212        &dspic_post_test,                               \
 213        NULL,                                           \
 214        NULL,                                           \
 215        CONFIG_SYS_POST_BSPEC2                          \
 216        }
 217
 218#define CONFIG_POST_BSPEC3    {                         \
 219        "FPGA test",                                    \
 220        "fpga",                                         \
 221        "This test checks FPGA registers and memory.",  \
 222        POST_RAM | POST_ALWAYS | POST_MANUAL,           \
 223        &fpga_post_test,                                \
 224        NULL,                                           \
 225        NULL,                                           \
 226        CONFIG_SYS_POST_BSPEC3                          \
 227        }
 228
 229#define CONFIG_POST_BSPEC4    {                         \
 230        "GDC test",                                     \
 231        "gdc",                                          \
 232        "This test checks GDC registers and memory.",   \
 233        POST_RAM | POST_ALWAYS | POST_MANUAL,\
 234        &gdc_post_test,                                 \
 235        NULL,                                           \
 236        NULL,                                           \
 237        CONFIG_SYS_POST_BSPEC4                          \
 238        }
 239
 240#define CONFIG_POST_BSPEC5    {                         \
 241        "SYSMON1 test",                                 \
 242        "sysmon1",                                      \
 243        "This test checks GPIO_62_EPX pin indicating power failure.",   \
 244        POST_RAM | POST_MANUAL | POST_NORMAL | POST_SLOWTEST,   \
 245        &sysmon1_post_test,                             \
 246        NULL,                                           \
 247        NULL,                                           \
 248        CONFIG_SYS_POST_BSPEC5                          \
 249        }
 250
 251#define CONFIG_SYS_POST_CACHE_ADDR      0x7fff0000 /* free virtual address      */
 252#define CONFIG_LOGBUFFER
 253/* Reserve GPT0_COMP1-COMP5 for logbuffer header */
 254#define CONFIG_ALT_LH_ADDR      (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP1)
 255#define CONFIG_ALT_LB_ADDR      (CONFIG_SYS_OCM_BASE)
 256
 257/*
 258 * I2C
 259 */
 260#define CONFIG_SYS_I2C
 261#define CONFIG_SYS_I2C_PPC4XX
 262#define CONFIG_SYS_I2C_PPC4XX_CH0
 263#define CONFIG_SYS_I2C_PPC4XX_SPEED_0           100000
 264#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0           0x7F
 265
 266#define CONFIG_SYS_I2C_RTC_ADDR 0x51    /* RTC                          */
 267#define CONFIG_SYS_I2C_EEPROM_CPU_ADDR  0x52    /* EEPROM          (CPU Modul)  */
 268#define CONFIG_SYS_I2C_EEPROM_MB_ADDR   0x53    /* EEPROM AT24C128 (MainBoard)  */
 269#define CONFIG_SYS_I2C_DSPIC_ADDR       0x54    /* dsPIC                        */
 270#define CONFIG_SYS_I2C_DSPIC_2_ADDR     0x55    /* dsPIC                        */
 271#define CONFIG_SYS_I2C_DSPIC_KEYB_ADDR  0x56    /* dsPIC                        */
 272#define CONFIG_SYS_I2C_DSPIC_IO_ADDR    0x57    /* dsPIC                        */
 273
 274#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2        /* Bytes of address             */
 275#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6     /* The Atmel AT24C128 has       */
 276                                        /* 64 byte page write mode using*/
 277                                        /* last 6 bits of the address   */
 278#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10   /* and takes up to 10 msec */
 279#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
 280
 281#define CONFIG_RTC_PCF8563                      /* enable Philips PCF8563 RTC   */
 282#define CONFIG_SYS_I2C_RTC_ADDR         0x51    /* Philips PCF8563 RTC address  */
 283#define CONFIG_SYS_I2C_KEYBD_ADDR       0x56    /* PIC LWE keyboard             */
 284#define CONFIG_SYS_I2C_DSPIC_IO_ADDR    0x57    /* PIC I/O addr               */
 285
 286#define CONFIG_SYS_POST_I2C_ADDRS       {CONFIG_SYS_I2C_RTC_ADDR,       \
 287                                         CONFIG_SYS_I2C_EEPROM_CPU_ADDR,\
 288                                         CONFIG_SYS_I2C_EEPROM_MB_ADDR, \
 289                                         CONFIG_SYS_I2C_DSPIC_ADDR,     \
 290                                         CONFIG_SYS_I2C_DSPIC_2_ADDR,   \
 291                                         CONFIG_SYS_I2C_DSPIC_KEYB_ADDR,\
 292                                         CONFIG_SYS_I2C_DSPIC_IO_ADDR }
 293
 294/* Update size in "reg" property of NOR FLASH device tree nodes */
 295#define CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
 296
 297#define CONFIG_POST_KEY_MAGIC   "3C+3E" /* press F3 + F5 keys to force POST */
 298
 299#define CONFIG_PREBOOT          "setenv bootdelay 15"
 300
 301#undef  CONFIG_BOOTARGS
 302
 303#define CONFIG_EXTRA_ENV_SETTINGS                                       \
 304        "hostname=lwmon5\0"                                             \
 305        "netdev=eth0\0"                                                 \
 306        "unlock=yes\0"                                                  \
 307        "logversion=2\0"                                                \
 308        "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 309                "nfsroot=${serverip}:${rootpath}\0"                     \
 310        "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 311        "addip=setenv bootargs ${bootargs} "                            \
 312                "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 313                ":${hostname}:${netdev}:off panic=1\0"                  \
 314        "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0"\
 315        "addmisc=setenv bootargs ${bootargs} rtc-pcf8563.probe=0,0x51\0"\
 316        "flash_nfs=run nfsargs addip addtty addmisc;"                   \
 317                "bootm ${kernel_addr}\0"                                \
 318        "flash_self=run ramargs addip addtty addmisc;"                  \
 319                "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 320        "net_nfs=tftp 200000 ${bootfile};"                              \
 321                "run nfsargs addip addtty addmisc;bootm\0"              \
 322        "rootpath=/opt/eldk/ppc_4xxFP\0"                                \
 323        "bootfile=/tftpboot/lwmon5/uImage\0"                            \
 324        "kernel_addr=FC000000\0"                                        \
 325        "ramdisk_addr=FC180000\0"                                       \
 326        "load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0"           \
 327        "update=protect off FFF80000 FFFFFFFF;era FFF80000 FFFFFFFF;"   \
 328                "cp.b 200000 FFF80000 80000\0"                          \
 329        "upd=run load update\0"                                         \
 330        "lwe_env=tftp 200000 /tftpboot.dev/lwmon5/env_uboot.bin;"       \
 331                "autoscr 200000\0"                                      \
 332        ""
 333#define CONFIG_BOOTCOMMAND      "run flash_self"
 334
 335
 336#define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 337#define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
 338
 339#define CONFIG_PPC4xx_EMAC
 340#define CONFIG_IBM_EMAC4_V4     1
 341#define CONFIG_MII              1       /* MII PHY management           */
 342#define CONFIG_PHY_ADDR         3       /* PHY address, See schematics  */
 343
 344#define CONFIG_PHY_RESET        1       /* reset phy upon startup         */
 345#define CONFIG_PHY_RESET_DELAY  300
 346
 347#define CONFIG_HAS_ETH0
 348#define CONFIG_SYS_RX_ETH_BUFFER        32      /* Number of ethernet rx buffers & descriptors */
 349
 350#define CONFIG_HAS_ETH1         1       /* add support for "eth1addr"   */
 351#define CONFIG_PHY1_ADDR        1
 352
 353/* Video console */
 354#define CONFIG_VIDEO_MB862xx
 355#define CONFIG_VIDEO_MB862xx_ACCEL
 356#define CONFIG_VIDEO_LOGO
 357#define VIDEO_FB_16BPP_PIXEL_SWAP
 358#define VIDEO_FB_16BPP_WORD_SWAP
 359
 360#define CONFIG_SPLASH_SCREEN
 361
 362/*
 363 * USB/EHCI
 364 */
 365#define CONFIG_USB_EHCI                 /* Enable EHCI USB support      */
 366#define CONFIG_USB_EHCI_PPC4XX          /* on PPC4xx platform           */
 367#define CONFIG_SYS_PPC4XX_USB_ADDR      0xe0000300
 368#define CONFIG_EHCI_MMIO_BIG_ENDIAN
 369#define CONFIG_EHCI_DESC_BIG_ENDIAN
 370#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* re-init HCD after CMD_RESET */
 371
 372/* Partitions */
 373
 374/*
 375 * BOOTP options
 376 */
 377#define CONFIG_BOOTP_BOOTFILESIZE
 378#define CONFIG_BOOTP_BOOTPATH
 379#define CONFIG_BOOTP_GATEWAY
 380#define CONFIG_BOOTP_HOSTNAME
 381
 382/*
 383 * Command line configuration.
 384 */
 385#define CONFIG_CMD_EEPROM
 386#define CONFIG_CMD_IRQ
 387#define CONFIG_CMD_REGINFO
 388#define CONFIG_CMD_SDRAM
 389
 390#ifdef CONFIG_440EPX
 391#endif
 392
 393/*
 394 * Miscellaneous configurable options
 395 */
 396#define CONFIG_SUPPORT_VFAT
 397
 398#define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 399
 400#if defined(CONFIG_CMD_KGDB)
 401#define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size      */
 402#else
 403#define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size      */
 404#endif
 405#define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 406#define CONFIG_SYS_MAXARGS              16      /* max number of command args   */
 407#define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size  */
 408
 409#define CONFIG_SYS_MEMTEST_START        0x0400000 /* memtest works on           */
 410#define CONFIG_SYS_MEMTEST_END          0x0C00000 /* 4 ... 12 MB in DRAM        */
 411
 412#define CONFIG_SYS_LOAD_ADDR            0x100000  /* default load address       */
 413#define CONFIG_SYS_EXTBDINFO            1       /* To use extended board_into (bd_t) */
 414
 415#define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 416#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
 417
 418#ifndef DEBUG
 419#define CONFIG_HW_WATCHDOG      1       /* Use external HW-Watchdog     */
 420#endif
 421#define CONFIG_WD_PERIOD        40000   /* in usec */
 422#define CONFIG_WD_MAX_RATE      66600   /* in ticks */
 423
 424/*
 425 * For booting Linux, the board info and command line data
 426 * have to be in the first 16 MB of memory, since this is
 427 * the maximum mapped by the 40x Linux kernel during initialization.
 428 */
 429#define CONFIG_SYS_BOOTMAPSZ            (16 << 20) /* Initial Memory map for Linux */
 430#define CONFIG_SYS_BOOTM_LEN            (16 << 20) /* Increase max gunzip size */
 431
 432/*
 433 * External Bus Controller (EBC) Setup
 434 */
 435#define CONFIG_SYS_FLASH                CONFIG_SYS_FLASH_BASE
 436
 437/* Memory Bank 0 (NOR-FLASH) initialization                                     */
 438#define CONFIG_SYS_EBC_PB0AP            0x03000280
 439#define CONFIG_SYS_EBC_PB0CR            (CONFIG_SYS_FLASH | 0xfc000)
 440
 441/* Memory Bank 1 (Lime) initialization                                          */
 442#define CONFIG_SYS_EBC_PB1AP            0x01004380
 443#define CONFIG_SYS_EBC_PB1CR            (CONFIG_SYS_LIME_BASE_0 | 0xbc000)
 444
 445/* Memory Bank 2 (FPGA) initialization                                          */
 446#define CONFIG_SYS_EBC_PB2AP            0x01004400
 447#define CONFIG_SYS_EBC_PB2CR            (CONFIG_SYS_FPGA_BASE_0 | 0x1c000)
 448
 449/* Memory Bank 3 (FPGA2) initialization                                         */
 450#define CONFIG_SYS_EBC_PB3AP            0x01004400
 451#define CONFIG_SYS_EBC_PB3CR            (CONFIG_SYS_FPGA_BASE_1 | 0x1c000)
 452
 453#define CONFIG_SYS_EBC_CFG              0xb8400000
 454
 455/*
 456 * Graphics (Fujitsu Lime)
 457 */
 458/* SDRAM Clock frequency adjustment register */
 459#define CONFIG_SYS_LIME_SDRAM_CLOCK     0xC1FC0038
 460#if 1 /* 133MHz is not tested enough, use 100MHz for now */
 461/* Lime Clock frequency is to set 100MHz */
 462#define CONFIG_SYS_LIME_CLOCK_100MHZ    0x00000
 463#else
 464/* Lime Clock frequency for 133MHz */
 465#define CONFIG_SYS_LIME_CLOCK_133MHZ    0x10000
 466#endif
 467
 468/* SDRAM Parameter register */
 469#define CONFIG_SYS_LIME_MMR             0xC1FCFFFC
 470/*
 471 * SDRAM parameter value; was 0x414FB7F2, caused several vertical bars
 472 * and pixel flare on display when 133MHz was configured. According to
 473 * SDRAM chip datasheet CAS Latency is 3 for 133MHz and -75 Speed
 474 * Grade
 475 */
 476#ifdef CONFIG_SYS_LIME_CLOCK_133MHZ
 477#define CONFIG_SYS_MB862xx_MMR  0x414FB7F3
 478#define CONFIG_SYS_MB862xx_CCF  CONFIG_SYS_LIME_CLOCK_133MHZ
 479#else
 480#define CONFIG_SYS_MB862xx_MMR  0x414FB7F2
 481#define CONFIG_SYS_MB862xx_CCF  CONFIG_SYS_LIME_CLOCK_100MHZ
 482#endif
 483
 484/*
 485 * GPIO Setup
 486 */
 487#define CONFIG_SYS_GPIO_PHY1_RST        12
 488#define CONFIG_SYS_GPIO_FLASH_WP        14
 489#define CONFIG_SYS_GPIO_PHY0_RST        22
 490#define CONFIG_SYS_GPIO_PERM_VOLT_FEED  49
 491#define CONFIG_SYS_GPIO_DSPIC_READY     51
 492#define CONFIG_SYS_GPIO_CAN_ENABLE      53
 493#define CONFIG_SYS_GPIO_LSB_ENABLE      54
 494#define CONFIG_SYS_GPIO_EEPROM_EXT_WP   55
 495#define CONFIG_SYS_GPIO_HIGHSIDE        56
 496#define CONFIG_SYS_GPIO_EEPROM_INT_WP   57
 497#define CONFIG_SYS_GPIO_BOARD_RESET     58
 498#define CONFIG_SYS_GPIO_LIME_S          59
 499#define CONFIG_SYS_GPIO_LIME_RST        60
 500#define CONFIG_SYS_GPIO_SYSMON_STATUS   62
 501#define CONFIG_SYS_GPIO_WATCHDOG        63
 502
 503#define GPIO49_VAL      1
 504
 505/*
 506 * PPC440 GPIO Configuration
 507 */
 508#define CONFIG_SYS_4xx_GPIO_TABLE { /*    Out             GPIO  Alternate1      Alternate2      Alternate3 */ \
 509{                                                                                       \
 510/* GPIO Core 0 */                                                                       \
 511{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7)     DMA_REQ(2)      */      \
 512{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6)     DMA_ACK(2)      */      \
 513{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5)     DMA_EOT/TC(2)   */      \
 514{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4)     DMA_REQ(3)      */      \
 515{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3)     DMA_ACK(3)      */      \
 516{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2)     DMA_EOT/TC(3)   */      \
 517{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1)                     */      \
 518{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 EBC_CS_N(2)                     */      \
 519{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS_N(3)                     */      \
 520{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS_N(4)                     */      \
 521{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5)                    */      \
 522{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR                    */      \
 523{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO12                                */      \
 524{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO13                                */      \
 525{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14                                */      \
 526{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO15                                */      \
 527{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMCTxD(4)                      */      \
 528{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMCTxD(5)                      */      \
 529{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMCTxD(6)                      */      \
 530{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMCTxD(7)                      */      \
 531{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 RejectPkt0                     */      \
 532{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 RejectPkt1                     */      \
 533{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO22                                */      \
 534{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 SCPD0                          */      \
 535{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 GMCTxD(2)                      */      \
 536{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 GMCTxD(3)                      */      \
 537{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26                                */      \
 538{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ    USB2D_RXERROR   */      \
 539{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO28                USB2D_TXVALID   */      \
 540{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO29 EBC_EXT_HDLA   USB2D_PAD_SUSPNDM */    \
 541{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO30 EBC_EXT_ACK    USB2D_XCVRSELECT*/      \
 542{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/      \
 543},                                                                                      \
 544{                                                                                       \
 545/* GPIO Core 1 */                                                                       \
 546{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO32 USB2D_OPMODE0  EBC_DATA(2)     */      \
 547{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO33 USB2D_OPMODE1  EBC_DATA(3)     */      \
 548{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_0}, /* GPIO34 UART0_DCD_N    UART1_DSR_CTS_N UART2_SOUT*/ \
 549{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
 550{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N EBC_DATA(0)   UART3_SIN*/ \
 551{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N    EBC_DATA(1)     UART3_SOUT*/ \
 552{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO38 UART0_DTR_N    UART1_SOUT      */      \
 553{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N     UART1_SIN       */      \
 554{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0)                     */      \
 555{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1)                     */      \
 556{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2)                     */      \
 557{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3)                     */      \
 558{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4)     DMA_ACK(1)      */      \
 559{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6)     DMA_EOT/TC(1)   */      \
 560{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7)     DMA_REQ(0)      */      \
 561{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8)     DMA_ACK(0)      */      \
 562{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9)     DMA_EOT/TC(0)   */      \
 563{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO49_VAL}, /* GPIO49  Unselect via TraceSelect Bit  */      \
 564{GPIO1_BASE, GPIO_IN,  GPIO_SEL , GPIO_OUT_0}, /* GPIO50  Unselect via TraceSelect Bit  */      \
 565{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51  Unselect via TraceSelect Bit  */      \
 566{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52  Unselect via TraceSelect Bit  */      \
 567{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO53  Unselect via TraceSelect Bit  */      \
 568{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO54  Unselect via TraceSelect Bit  */      \
 569{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO55  Unselect via TraceSelect Bit  */      \
 570{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO56  Unselect via TraceSelect Bit  */      \
 571{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO57  Unselect via TraceSelect Bit  */      \
 572{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO58  Unselect via TraceSelect Bit  */      \
 573{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO59  Unselect via TraceSelect Bit  */      \
 574{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO60  Unselect via TraceSelect Bit  */      \
 575{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61  Unselect via TraceSelect Bit  */      \
 576{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62  Unselect via TraceSelect Bit  */      \
 577{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO63  Unselect via TraceSelect Bit  */      \
 578}                                                                                       \
 579}
 580
 581#if defined(CONFIG_CMD_KGDB)
 582#define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 583#endif
 584
 585#endif  /* __CONFIG_H */
 586