LXR uboot/include/configs/maxbcm.h

   1/*
   2 * Copyright (C) 2014 Stefan Roese <sr@denx.de>
   3 *
   4 * SPDX-License-Identifier:     GPL-2.0+
   5 */
   6
   7#ifndef _CONFIG_DB_MV7846MP_GP_H
   8#define _CONFIG_DB_MV7846MP_GP_H
   9
  10/*
  11 * High Level Configuration Options (easy to change)
  12 */
  13#define CONFIG_DISPLAY_BOARDINFO_LATE
  14
  15/*
  16 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
  17 * for DDR ECC byte filling in the SPL before loading the main
  18 * U-Boot into it.
  19 */
  20#define CONFIG_SYS_TEXT_BASE    0x00800000
  21#define CONFIG_SYS_TCLK         250000000       /* 250MHz */
  22
  23/*
  24 * Commands configuration
  25 */
  26#define CONFIG_CMD_ENV
  27
  28/* I2C */
  29#define CONFIG_SYS_I2C
  30#define CONFIG_SYS_I2C_MVTWSI
  31#define CONFIG_I2C_MVTWSI_BASE0         MVEBU_TWSI_BASE
  32#define CONFIG_SYS_I2C_SLAVE            0x0
  33#define CONFIG_SYS_I2C_SPEED            100000
  34
  35/* SPI NOR flash default params, used by sf commands */
  36#define CONFIG_SF_DEFAULT_SPEED         1000000
  37#define CONFIG_SF_DEFAULT_MODE          SPI_MODE_3
  38
  39/* Environment in SPI NOR flash */
  40#define CONFIG_ENV_IS_IN_SPI_FLASH
  41#define CONFIG_ENV_OFFSET               (1 << 20) /* 1MiB in */
  42#define CONFIG_ENV_SIZE                 (64 << 10) /* 64KiB */
  43#define CONFIG_ENV_SECT_SIZE            (64 << 10) /* 64KiB sectors */
  44
  45#define CONFIG_PHY_MARVELL              /* there is a marvell phy */
  46#define PHY_ANEG_TIMEOUT        8000    /* PHY needs a longer aneg time */
  47
  48#define CONFIG_SYS_ALT_MEMTEST
  49
  50/*
  51 * mv-common.h should be defined after CMD configs since it used them
  52 * to enable certain macros
  53 */
  54#include "mv-common.h"
  55
  56/*
  57 * Memory layout while starting into the bin_hdr via the
  58 * BootROM:
  59 *
  60 * 0x4000.4000 - 0x4003.4000    headers space (192KiB)
  61 * 0x4000.4030                  bin_hdr start address
  62 * 0x4003.4000 - 0x4004.7c00    BootROM memory allocations (15KiB)
  63 * 0x4007.fffc                  BootROM stack top
  64 *
  65 * The address space between 0x4007.fffc and 0x400f.fff is not locked in
  66 * L2 cache thus cannot be used.
  67 */
  68
  69/* SPL */
  70/* Defines for SPL */
  71#define CONFIG_SPL_FRAMEWORK
  72#define CONFIG_SPL_TEXT_BASE            0x40004030
  73#define CONFIG_SPL_MAX_SIZE             ((128 << 10) - 0x4030)
  74
  75#define CONFIG_SPL_BSS_START_ADDR       (0x40000000 + (128 << 10))
  76#define CONFIG_SPL_BSS_MAX_SIZE         (16 << 10)
  77
  78#ifdef CONFIG_SPL_BUILD
  79#define CONFIG_SYS_MALLOC_SIMPLE
  80#endif
  81
  82#define CONFIG_SPL_STACK                (0x40000000 + ((192 - 16) << 10))
  83#define CONFIG_SPL_BOOTROM_SAVE         (CONFIG_SPL_STACK + 4)
  84
  85/* SPL related SPI defines */
  86#define CONFIG_SPL_SPI_LOAD
  87#define CONFIG_SYS_SPI_U_BOOT_OFFS      0x20000
  88
  89/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
  90#define CONFIG_DDR_FIXED_SIZE           (1 << 20)       /* 1GiB */
  91#define CONFIG_BOARD_ECC_SUPPORT        /* this board supports ECC */
  92
  93#endif /* _CONFIG_DB_MV7846MP_GP_H */
  94