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15#ifndef __CONFIG_H
16#define __CONFIG_H
17
18
19
20
21#define CONFIG_E300 1
22#define CONFIG_MPC834x 1
23#define CONFIG_MPC8349 1
24#define CONFIG_SBC8349 1
25
26#define CONFIG_SYS_TEXT_BASE 0xFF800000
27
28
29#undef CONFIG_MPC83XX_PCI2
30
31
32
33
34
35
36
37#ifdef CONFIG_PCI_33M
38#define CONFIG_83XX_CLKIN 33000000
39#else
40#define CONFIG_83XX_CLKIN 66000000
41#endif
42
43#ifndef CONFIG_SYS_CLK_FREQ
44#ifdef CONFIG_PCI_33M
45#define CONFIG_SYS_CLK_FREQ 33000000
46#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1
47#else
48#define CONFIG_SYS_CLK_FREQ 66000000
49#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1
50#endif
51#endif
52
53#define CONFIG_SYS_IMMR 0xE0000000
54
55#undef CONFIG_SYS_DRAM_TEST
56#define CONFIG_SYS_MEMTEST_START 0x00000000
57#define CONFIG_SYS_MEMTEST_END 0x00100000
58
59
60
61
62#undef CONFIG_DDR_ECC
63#undef CONFIG_DDR_ECC_CMD
64#define CONFIG_SPD_EEPROM
65#define CONFIG_SYS_83XX_DDR_USES_CS0
66
67
68
69
70
71
72
73
74
75
76
77#undef CONFIG_DDR_32BIT
78
79#define CONFIG_SYS_DDR_BASE 0x00000000
80#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
81#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
82#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
83 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
84#define CONFIG_DDR_2T_TIMING
85
86#if defined(CONFIG_SPD_EEPROM)
87
88
89
90#define SPD_EEPROM_ADDRESS 0x52
91
92#else
93
94
95
96
97#define CONFIG_SYS_DDR_SIZE 256
98#define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \
99 | CSCONFIG_ROW_BIT_13 \
100 | CSCONFIG_COL_BIT_10)
101#define CONFIG_SYS_DDR_TIMING_1 0x36332321
102#define CONFIG_SYS_DDR_TIMING_2 0x00000800
103#define CONFIG_SYS_DDR_CONTROL 0xc2000000
104#define CONFIG_SYS_DDR_INTERVAL 0x04060100
105
106#if defined(CONFIG_DDR_32BIT)
107
108
109#define CONFIG_SYS_DDR_MODE 0x00000023
110#else
111
112
113#define CONFIG_SYS_DDR_MODE 0x00000022
114#endif
115#endif
116
117
118
119
120#define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000
121#define CONFIG_SYS_LBC_SDRAM_SIZE 64
122
123
124
125
126#define CONFIG_SYS_FLASH_CFI
127#define CONFIG_FLASH_CFI_DRIVER
128#define CONFIG_SYS_FLASH_BASE 0xFF800000
129#define CONFIG_SYS_FLASH_SIZE 8
130
131
132#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
133 | BR_PS_16 \
134 | BR_MS_GPCM \
135 | BR_V)
136
137#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
138 | OR_GPCM_XAM \
139 | OR_GPCM_CSNT \
140 | OR_GPCM_ACS_DIV2 \
141 | OR_GPCM_XACS \
142 | OR_GPCM_SCY_15 \
143 | OR_GPCM_TRLX_SET \
144 | OR_GPCM_EHTR_SET \
145 | OR_GPCM_EAD)
146
147
148
149#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
150#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB)
151
152#define CONFIG_SYS_MAX_FLASH_BANKS 1
153#define CONFIG_SYS_MAX_FLASH_SECT 64
154
155#undef CONFIG_SYS_FLASH_CHECKSUM
156#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
157#define CONFIG_SYS_FLASH_WRITE_TOUT 500
158
159#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
160
161#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
162#define CONFIG_SYS_RAMBOOT
163#else
164#undef CONFIG_SYS_RAMBOOT
165#endif
166
167#define CONFIG_SYS_INIT_RAM_LOCK 1
168
169#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000
170
171#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
172
173#define CONFIG_SYS_GBL_DATA_OFFSET \
174 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
175#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
176
177#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
178#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
179
180
181
182
183
184
185
186#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
187#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
188#define CONFIG_SYS_LBC_LBCR 0x00000000
189
190#undef CONFIG_SYS_LB_SDRAM
191
192#ifdef CONFIG_SYS_LB_SDRAM
193
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206
207
208
209#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LBC_SDRAM_BASE \
210 | BR_PS_32 \
211 | BR_MS_SDRAM \
212 | BR_V)
213
214#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE
215#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB)
216
217
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220
221
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227
228
229
230
231#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_LBC_SDRAM_SIZE) \
232 | OR_SDRAM_XAM \
233 | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \
234 | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \
235 | OR_SDRAM_EAD)
236
237
238
239#define CONFIG_SYS_LBC_LSRT 0x32000000
240
241#define CONFIG_SYS_LBC_MRTPR 0x20000000
242
243#define CONFIG_SYS_LBC_LSDMR_COMMON (LSDMR_RFEN \
244 | LSDMR_BSMA1516 \
245 | LSDMR_RFCR8 \
246 | LSDMR_PRETOACT6 \
247 | LSDMR_ACTTORW3 \
248 | LSDMR_BL8 \
249 | LSDMR_WRC3 \
250 | LSDMR_CL3)
251
252
253
254
255#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
256#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
257#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
258#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
259#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
260#endif
261
262
263
264
265#define CONFIG_CONS_INDEX 1
266#define CONFIG_SYS_NS16550_SERIAL
267#define CONFIG_SYS_NS16550_REG_SIZE 1
268#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
269
270#define CONFIG_SYS_BAUDRATE_TABLE \
271 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
272
273#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
274#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
275
276#define CONFIG_CMDLINE_EDITING 1
277#define CONFIG_AUTO_COMPLETE
278
279
280#define CONFIG_SYS_I2C
281#define CONFIG_SYS_I2C_FSL
282#define CONFIG_SYS_FSL_I2C_SPEED 400000
283#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
284#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
285#define CONFIG_SYS_FSL_I2C2_SPEED 400000
286#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
287#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
288#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69}, {1, 0x69} }
289
290
291
292#define CONFIG_SYS_TSEC1_OFFSET 0x24000
293#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
294#define CONFIG_SYS_TSEC2_OFFSET 0x25000
295#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
296
297
298
299
300
301#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
302#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
303#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000
304#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
305#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
306#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000
307#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
308#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
309#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000
310
311#define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
312#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
313#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000
314#define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
315#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
316#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000
317#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
318#define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
319#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000
320
321#if defined(CONFIG_PCI)
322
323#define PCI_64BIT
324#define PCI_ONE_PCI1
325#if defined(PCI_64BIT)
326#undef PCI_ALL_PCI1
327#undef PCI_TWO_PCI1
328#undef PCI_ONE_PCI1
329#endif
330
331#undef CONFIG_EEPRO100
332#undef CONFIG_TULIP
333
334#if !defined(CONFIG_PCI_PNP)
335 #define PCI_ENET0_IOADDR 0xFIXME
336 #define PCI_ENET0_MEMADDR 0xFIXME
337 #define PCI_IDSEL_NUMBER 0xFIXME
338#endif
339
340#undef CONFIG_PCI_SCAN_SHOW
341#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057
342
343#endif
344
345
346
347
348#define CONFIG_TSEC_ENET
349
350#if defined(CONFIG_TSEC_ENET)
351
352#define CONFIG_TSEC1 1
353#define CONFIG_TSEC1_NAME "TSEC0"
354#define CONFIG_TSEC2 1
355#define CONFIG_TSEC2_NAME "TSEC1"
356#define CONFIG_PHY_BCM5421S 1
357#define TSEC1_PHY_ADDR 0x19
358#define TSEC2_PHY_ADDR 0x1a
359#define TSEC1_PHYIDX 0
360#define TSEC2_PHYIDX 0
361#define TSEC1_FLAGS TSEC_GIGABIT
362#define TSEC2_FLAGS TSEC_GIGABIT
363
364
365#define CONFIG_ETHPRIME "TSEC0"
366
367#endif
368
369
370
371
372#ifndef CONFIG_SYS_RAMBOOT
373 #define CONFIG_ENV_IS_IN_FLASH 1
374 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
375 #define CONFIG_ENV_SECT_SIZE 0x20000
376 #define CONFIG_ENV_SIZE 0x2000
377
378
379#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
380#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
381
382#else
383 #define CONFIG_ENV_IS_NOWHERE 1
384 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
385 #define CONFIG_ENV_SIZE 0x2000
386#endif
387
388#define CONFIG_LOADS_ECHO 1
389#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
390
391
392
393
394#define CONFIG_BOOTP_BOOTFILESIZE
395#define CONFIG_BOOTP_BOOTPATH
396#define CONFIG_BOOTP_GATEWAY
397#define CONFIG_BOOTP_HOSTNAME
398
399
400
401
402
403#if defined(CONFIG_PCI)
404 #define CONFIG_CMD_PCI
405#endif
406
407#undef CONFIG_WATCHDOG
408
409
410
411
412#define CONFIG_SYS_LONGHELP
413#define CONFIG_SYS_LOAD_ADDR 0x2000000
414
415#if defined(CONFIG_CMD_KGDB)
416 #define CONFIG_SYS_CBSIZE 1024
417#else
418 #define CONFIG_SYS_CBSIZE 256
419#endif
420
421
422#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
423#define CONFIG_SYS_MAXARGS 16
424
425#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
426
427
428
429
430
431
432
433#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
434
435#define CONFIG_SYS_RCWH_PCIHOST 0x80000000
436
437#if 1
438#define CONFIG_SYS_HRCW_LOW (\
439 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
440 HRCWL_DDR_TO_SCB_CLK_1X1 |\
441 HRCWL_CSB_TO_CLKIN |\
442 HRCWL_VCO_1X2 |\
443 HRCWL_CORE_TO_CSB_2X1)
444#elif 0
445#define CONFIG_SYS_HRCW_LOW (\
446 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
447 HRCWL_DDR_TO_SCB_CLK_1X1 |\
448 HRCWL_CSB_TO_CLKIN |\
449 HRCWL_VCO_1X4 |\
450 HRCWL_CORE_TO_CSB_3X1)
451#elif 0
452#define CONFIG_SYS_HRCW_LOW (\
453 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
454 HRCWL_DDR_TO_SCB_CLK_1X1 |\
455 HRCWL_CSB_TO_CLKIN |\
456 HRCWL_VCO_1X4 |\
457 HRCWL_CORE_TO_CSB_2X1)
458#elif 0
459#define CONFIG_SYS_HRCW_LOW (\
460 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
461 HRCWL_DDR_TO_SCB_CLK_1X1 |\
462 HRCWL_CSB_TO_CLKIN |\
463 HRCWL_VCO_1X4 |\
464 HRCWL_CORE_TO_CSB_1X1)
465#elif 0
466#define CONFIG_SYS_HRCW_LOW (\
467 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
468 HRCWL_DDR_TO_SCB_CLK_1X1 |\
469 HRCWL_CSB_TO_CLKIN |\
470 HRCWL_VCO_1X4 |\
471 HRCWL_CORE_TO_CSB_1X1)
472#endif
473
474#if defined(PCI_64BIT)
475#define CONFIG_SYS_HRCW_HIGH (\
476 HRCWH_PCI_HOST |\
477 HRCWH_64_BIT_PCI |\
478 HRCWH_PCI1_ARBITER_ENABLE |\
479 HRCWH_PCI2_ARBITER_DISABLE |\
480 HRCWH_CORE_ENABLE |\
481 HRCWH_FROM_0X00000100 |\
482 HRCWH_BOOTSEQ_DISABLE |\
483 HRCWH_SW_WATCHDOG_DISABLE |\
484 HRCWH_ROM_LOC_LOCAL_16BIT |\
485 HRCWH_TSEC1M_IN_GMII |\
486 HRCWH_TSEC2M_IN_GMII)
487#else
488#define CONFIG_SYS_HRCW_HIGH (\
489 HRCWH_PCI_HOST |\
490 HRCWH_32_BIT_PCI |\
491 HRCWH_PCI1_ARBITER_ENABLE |\
492 HRCWH_PCI2_ARBITER_ENABLE |\
493 HRCWH_CORE_ENABLE |\
494 HRCWH_FROM_0X00000100 |\
495 HRCWH_BOOTSEQ_DISABLE |\
496 HRCWH_SW_WATCHDOG_DISABLE |\
497 HRCWH_ROM_LOC_LOCAL_16BIT |\
498 HRCWH_TSEC1M_IN_GMII |\
499 HRCWH_TSEC2M_IN_GMII)
500#endif
501
502
503#define CONFIG_SYS_SICRH 0
504#define CONFIG_SYS_SICRL SICRL_LDP_A
505
506#define CONFIG_SYS_HID0_INIT 0x000000000
507#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \
508 | HID0_ENABLE_INSTRUCTION_CACHE)
509
510
511
512
513
514
515#define CONFIG_SYS_HID2 HID2_HBE
516
517#define CONFIG_HIGH_BATS 1
518
519
520#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
521 | BATL_PP_RW \
522 | BATL_MEMCOHERENCE)
523#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
524 | BATU_BL_256M \
525 | BATU_VS \
526 | BATU_VP)
527
528
529#ifdef CONFIG_PCI
530#define CONFIG_PCI_INDIRECT_BRIDGE
531#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \
532 | BATL_PP_RW \
533 | BATL_MEMCOHERENCE)
534#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
535 | BATU_BL_256M \
536 | BATU_VS \
537 | BATU_VP)
538#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
539 | BATL_PP_RW \
540 | BATL_CACHEINHIBIT \
541 | BATL_GUARDEDSTORAGE)
542#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
543 | BATU_BL_256M \
544 | BATU_VS \
545 | BATU_VP)
546#else
547#define CONFIG_SYS_IBAT1L (0)
548#define CONFIG_SYS_IBAT1U (0)
549#define CONFIG_SYS_IBAT2L (0)
550#define CONFIG_SYS_IBAT2U (0)
551#endif
552
553#ifdef CONFIG_MPC83XX_PCI2
554#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \
555 | BATL_PP_RW \
556 | BATL_MEMCOHERENCE)
557#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \
558 | BATU_BL_256M \
559 | BATU_VS \
560 | BATU_VP)
561#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \
562 | BATL_PP_RW \
563 | BATL_CACHEINHIBIT \
564 | BATL_GUARDEDSTORAGE)
565#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \
566 | BATU_BL_256M \
567 | BATU_VS \
568 | BATU_VP)
569#else
570#define CONFIG_SYS_IBAT3L (0)
571#define CONFIG_SYS_IBAT3U (0)
572#define CONFIG_SYS_IBAT4L (0)
573#define CONFIG_SYS_IBAT4U (0)
574#endif
575
576
577#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
578 | BATL_PP_RW \
579 | BATL_CACHEINHIBIT \
580 | BATL_GUARDEDSTORAGE)
581#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
582 | BATU_BL_256M \
583 | BATU_VS \
584 | BATU_VP)
585
586
587#define CONFIG_SYS_IBAT6L (CONFIG_SYS_LBC_SDRAM_BASE \
588 | BATL_PP_RW \
589 | BATL_MEMCOHERENCE \
590 | BATL_GUARDEDSTORAGE)
591#define CONFIG_SYS_IBAT6U (CONFIG_SYS_LBC_SDRAM_BASE \
592 | BATU_BL_256M \
593 | BATU_VS \
594 | BATU_VP)
595
596#define CONFIG_SYS_IBAT7L (0)
597#define CONFIG_SYS_IBAT7U (0)
598
599#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
600#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
601#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
602#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
603#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
604#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
605#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
606#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
607#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
608#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
609#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
610#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
611#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
612#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
613#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
614#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
615
616#if defined(CONFIG_CMD_KGDB)
617#define CONFIG_KGDB_BAUDRATE 230400
618#endif
619
620
621
622
623#define CONFIG_ENV_OVERWRITE
624
625#if defined(CONFIG_TSEC_ENET)
626#define CONFIG_HAS_ETH0
627#define CONFIG_HAS_ETH1
628#endif
629
630#define CONFIG_HOSTNAME SBC8349
631#define CONFIG_ROOTPATH "/tftpboot/rootfs"
632#define CONFIG_BOOTFILE "uImage"
633
634
635#define CONFIG_LOADADDR 800000
636
637#undef CONFIG_BOOTARGS
638
639#define CONFIG_EXTRA_ENV_SETTINGS \
640 "netdev=eth0\0" \
641 "hostname=sbc8349\0" \
642 "nfsargs=setenv bootargs root=/dev/nfs rw " \
643 "nfsroot=${serverip}:${rootpath}\0" \
644 "ramargs=setenv bootargs root=/dev/ram rw\0" \
645 "addip=setenv bootargs ${bootargs} " \
646 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
647 ":${hostname}:${netdev}:off panic=1\0" \
648 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
649 "flash_nfs=run nfsargs addip addtty;" \
650 "bootm ${kernel_addr}\0" \
651 "flash_self=run ramargs addip addtty;" \
652 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
653 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
654 "bootm\0" \
655 "load=tftp 100000 /tftpboot/sbc8349/u-boot.bin\0" \
656 "update=protect off ff800000 ff83ffff; " \
657 "era ff800000 ff83ffff; cp.b 100000 ff800000 ${filesize}\0" \
658 "upd=run load update\0" \
659 "fdtaddr=780000\0" \
660 "fdtfile=sbc8349.dtb\0" \
661 ""
662
663#define CONFIG_NFSBOOTCOMMAND \
664 "setenv bootargs root=/dev/nfs rw " \
665 "nfsroot=$serverip:$rootpath " \
666 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
667 "$netdev:off " \
668 "console=$consoledev,$baudrate $othbootargs;" \
669 "tftp $loadaddr $bootfile;" \
670 "tftp $fdtaddr $fdtfile;" \
671 "bootm $loadaddr - $fdtaddr"
672
673#define CONFIG_RAMBOOTCOMMAND \
674 "setenv bootargs root=/dev/ram rw " \
675 "console=$consoledev,$baudrate $othbootargs;" \
676 "tftp $ramdiskaddr $ramdiskfile;" \
677 "tftp $loadaddr $bootfile;" \
678 "tftp $fdtaddr $fdtfile;" \
679 "bootm $loadaddr $ramdiskaddr $fdtaddr"
680
681#define CONFIG_BOOTCOMMAND "run flash_self"
682
683#endif
684