1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20#ifndef __CONFIG_H
21#define __CONFIG_H
22
23
24#define CONFIG_SBC8641D 1
25#define CONFIG_MP 1
26#define CONFIG_LINUX_RESET_VEC 0x100
27
28#define CONFIG_SYS_TEXT_BASE 0xfff00000
29
30#ifdef RUN_DIAG
31#define CONFIG_SYS_DIAG_ADDR 0xff800000
32#endif
33
34#define CONFIG_SYS_RESET_ADDRESS 0xfff00100
35
36
37
38
39
40#define CONFIG_SYS_SCRATCH_VA 0xe8000000
41
42#define CONFIG_SYS_SRIO
43#define CONFIG_SRIO1
44
45#define CONFIG_PCIE1 1
46#define CONFIG_PCIE2 1
47#define CONFIG_FSL_PCI_INIT 1
48#define CONFIG_PCI_INDIRECT_BRIDGE 1
49
50#define CONFIG_TSEC_ENET
51#define CONFIG_ENV_OVERWRITE
52
53#define CONFIG_BAT_RW 1
54#define CONFIG_HIGH_BATS 1
55
56#undef CONFIG_SPD_EEPROM
57#undef CONFIG_DDR_ECC
58#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
59#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
60#define CACHE_LINE_INTERLEAVING 0x20000000
61#define PAGE_INTERLEAVING 0x21000000
62#define BANK_INTERLEAVING 0x22000000
63#define SUPER_BANK_INTERLEAVING 0x23000000
64
65#define CONFIG_ALTIVEC 1
66
67
68
69
70#define CONFIG_SYS_L2
71#define L2_INIT 0
72#define L2_ENABLE (L2CR_L2E)
73
74#ifndef CONFIG_SYS_CLK_FREQ
75#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
76#endif
77
78#undef CONFIG_SYS_DRAM_TEST
79#define CONFIG_SYS_MEMTEST_START 0x00200000
80#define CONFIG_SYS_MEMTEST_END 0x00400000
81
82
83
84
85
86#define CONFIG_SYS_CCSRBAR 0xf8000000
87#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
88
89#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
90#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
91#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW
92
93
94
95
96#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
97#define CONFIG_SYS_DDR_SDRAM_BASE2 0x10000000
98#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
99#define CONFIG_SYS_SDRAM_BASE2 CONFIG_SYS_DDR_SDRAM_BASE2
100#define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000
101#define CONFIG_VERY_BIG_RAM
102
103#define CONFIG_DIMM_SLOTS_PER_CTLR 2
104#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
105
106#if defined(CONFIG_SPD_EEPROM)
107
108
109
110 #define SPD_EEPROM_ADDRESS1 0x51
111 #define SPD_EEPROM_ADDRESS2 0x52
112 #define SPD_EEPROM_ADDRESS3 0x53
113 #define SPD_EEPROM_ADDRESS4 0x54
114
115#else
116
117
118
119
120 #define CONFIG_SYS_SDRAM_SIZE 512
121
122 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F
123 #define CONFIG_SYS_DDR_CS1_BNDS 0x00000000
124 #define CONFIG_SYS_DDR_CS2_BNDS 0x00000000
125 #define CONFIG_SYS_DDR_CS3_BNDS 0x00000000
126 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102
127 #define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000
128 #define CONFIG_SYS_DDR_CS2_CONFIG 0x00000000
129 #define CONFIG_SYS_DDR_CS3_CONFIG 0x00000000
130 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
131 #define CONFIG_SYS_DDR_TIMING_0 0x00220802
132 #define CONFIG_SYS_DDR_TIMING_1 0x38377322
133 #define CONFIG_SYS_DDR_TIMING_2 0x002040c7
134 #define CONFIG_SYS_DDR_CFG_1A 0x43008008
135 #define CONFIG_SYS_DDR_CFG_2 0x24401000
136 #define CONFIG_SYS_DDR_MODE_1 0x23c00542
137 #define CONFIG_SYS_DDR_MODE_2 0x00000000
138 #define CONFIG_SYS_DDR_MODE_CTL 0x00000000
139 #define CONFIG_SYS_DDR_INTERVAL 0x05080100
140 #define CONFIG_SYS_DDR_DATA_INIT 0x00000000
141 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
142 #define CONFIG_SYS_DDR_CFG_1B 0xC3008008
143
144 #define CONFIG_SYS_DDR2_CS0_BNDS 0x0010001F
145 #define CONFIG_SYS_DDR2_CS1_BNDS 0x00000000
146 #define CONFIG_SYS_DDR2_CS2_BNDS 0x00000000
147 #define CONFIG_SYS_DDR2_CS3_BNDS 0x00000000
148 #define CONFIG_SYS_DDR2_CS0_CONFIG 0x80010102
149 #define CONFIG_SYS_DDR2_CS1_CONFIG 0x00000000
150 #define CONFIG_SYS_DDR2_CS2_CONFIG 0x00000000
151 #define CONFIG_SYS_DDR2_CS3_CONFIG 0x00000000
152 #define CONFIG_SYS_DDR2_EXT_REFRESH 0x00000000
153 #define CONFIG_SYS_DDR2_TIMING_0 0x00220802
154 #define CONFIG_SYS_DDR2_TIMING_1 0x38377322
155 #define CONFIG_SYS_DDR2_TIMING_2 0x002040c7
156 #define CONFIG_SYS_DDR2_CFG_1A 0x43008008
157 #define CONFIG_SYS_DDR2_CFG_2 0x24401000
158 #define CONFIG_SYS_DDR2_MODE_1 0x23c00542
159 #define CONFIG_SYS_DDR2_MODE_2 0x00000000
160 #define CONFIG_SYS_DDR2_MODE_CTL 0x00000000
161 #define CONFIG_SYS_DDR2_INTERVAL 0x05080100
162 #define CONFIG_SYS_DDR2_DATA_INIT 0x00000000
163 #define CONFIG_SYS_DDR2_CLK_CTRL 0x03800000
164 #define CONFIG_SYS_DDR2_CFG_1B 0xC3008008
165
166#endif
167
168
169
170
171
172
173
174#define CONFIG_SYS_FLASH_BASE 0xff000000
175
176
177#define CONFIG_SYS_BR0_PRELIM 0xff001001
178#define CONFIG_SYS_OR0_PRELIM 0xff006e65
179
180
181#define CONFIG_SYS_BR1_PRELIM 0xf0000801
182#define CONFIG_SYS_OR1_PRELIM 0xffff6e65
183
184
185#define CONFIG_SYS_BR2_PRELIM 0xf1000801
186#define CONFIG_SYS_OR2_PRELIM 0xfff06e65
187
188
189#define CONFIG_SYS_BR3_PRELIM 0xe0001861
190#define CONFIG_SYS_OR3_PRELIM 0xfc006cc0
191#define CONFIG_SYS_BR4_PRELIM 0xe4001861
192#define CONFIG_SYS_OR4_PRELIM 0xfc006cc0
193
194
195#define CONFIG_SYS_BR5_PRELIM 0xe8001001
196#define CONFIG_SYS_OR5_PRELIM 0xf8006e65
197
198
199#define CONFIG_SYS_BR6_PRELIM 0xf4000801
200#define CONFIG_SYS_OR6_PRELIM 0xfff06e65
201
202
203#define CONFIG_SYS_BR7_PRELIM 0xf2000801
204#define CONFIG_SYS_OR7_PRELIM 0xfff06e65
205
206#define CONFIG_SYS_MAX_FLASH_BANKS 1
207#define CONFIG_SYS_MAX_FLASH_SECT 131
208
209#undef CONFIG_SYS_FLASH_CHECKSUM
210#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
211#define CONFIG_SYS_FLASH_WRITE_TOUT 500
212#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
213#define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000
214
215#define CONFIG_FLASH_CFI_DRIVER
216#define CONFIG_SYS_FLASH_CFI
217#define CONFIG_SYS_WRITE_SWAPPED_DATA
218#define CONFIG_SYS_FLASH_EMPTY_INFO
219#define CONFIG_SYS_FLASH_PROTECTION
220
221#undef CONFIG_CLOCKS_IN_MHZ
222
223#define CONFIG_SYS_INIT_RAM_LOCK 1
224#ifndef CONFIG_SYS_INIT_RAM_LOCK
225#define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000
226#else
227#define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000
228#endif
229#define CONFIG_SYS_INIT_RAM_SIZE 0x4000
230
231#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
232#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
233
234#define CONFIG_SYS_MONITOR_LEN (384 * 1024)
235#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
236
237
238#define CONFIG_CONS_INDEX 1
239#define CONFIG_SYS_NS16550_SERIAL
240#define CONFIG_SYS_NS16550_REG_SIZE 1
241#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
242
243#define CONFIG_SYS_BAUDRATE_TABLE \
244 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
245
246#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
247#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
248
249
250
251
252#define CONFIG_SYS_I2C
253#define CONFIG_SYS_I2C_FSL
254#define CONFIG_SYS_FSL_I2C_SPEED 400000
255#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
256#define CONFIG_SYS_FSL_I2C_OFFSET 0x3100
257#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
258
259
260
261
262#define CONFIG_SYS_SRIO1_MEM_BASE 0xc0000000
263#define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BASE
264#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000
265
266
267
268
269
270#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
271#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
272#define CONFIG_SYS_PCIE1_MEM_VIRT CONFIG_SYS_PCIE1_MEM_BUS
273#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000
274#define CONFIG_SYS_PCIE1_IO_BUS 0xe2000000
275#define CONFIG_SYS_PCIE1_IO_PHYS CONFIG_SYS_PCIE1_IO_BUS
276#define CONFIG_SYS_PCIE1_IO_VIRT CONFIG_SYS_PCIE1_IO_BUS
277#define CONFIG_SYS_PCIE1_IO_SIZE 0x1000000
278
279#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
280#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS
281#define CONFIG_SYS_PCIE2_MEM_VIRT CONFIG_SYS_PCIE2_MEM_BUS
282#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
283#define CONFIG_SYS_PCIE2_IO_BUS 0xe3000000
284#define CONFIG_SYS_PCIE2_IO_PHYS CONFIG_SYS_PCIE2_IO_BUS
285#define CONFIG_SYS_PCIE2_IO_VIRT CONFIG_SYS_PCIE2_IO_BUS
286#define CONFIG_SYS_PCIE2_IO_SIZE 0x1000000
287
288#if defined(CONFIG_PCI)
289
290#define CONFIG_PCI_SCAN_SHOW
291
292#undef CONFIG_EEPRO100
293#undef CONFIG_TULIP
294
295#if !defined(CONFIG_PCI_PNP)
296 #define PCI_ENET0_IOADDR 0xe0000000
297 #define PCI_ENET0_MEMADDR 0xe0000000
298 #define PCI_IDSEL_NUMBER 0x0c
299#endif
300
301#define CONFIG_PCI_SCAN_SHOW
302
303#undef CONFIG_SCSI_AHCI
304
305#ifdef CONFIG_SCSI_AHCI
306#define CONFIG_SATA_ULI5288
307#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
308#define CONFIG_SYS_SCSI_MAX_LUN 1
309#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
310#define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
311#endif
312
313#endif
314
315#if defined(CONFIG_TSEC_ENET)
316
317
318
319#define CONFIG_TSEC1 1
320#define CONFIG_TSEC1_NAME "eTSEC1"
321#define CONFIG_TSEC2 1
322#define CONFIG_TSEC2_NAME "eTSEC2"
323#define CONFIG_TSEC3 1
324#define CONFIG_TSEC3_NAME "eTSEC3"
325#define CONFIG_TSEC4 1
326#define CONFIG_TSEC4_NAME "eTSEC4"
327
328#define TSEC1_PHY_ADDR 0x1F
329#define TSEC2_PHY_ADDR 0x00
330#define TSEC3_PHY_ADDR 0x01
331#define TSEC4_PHY_ADDR 0x02
332#define TSEC1_PHYIDX 0
333#define TSEC2_PHYIDX 0
334#define TSEC3_PHYIDX 0
335#define TSEC4_PHYIDX 0
336#define TSEC1_FLAGS TSEC_GIGABIT
337#define TSEC2_FLAGS TSEC_GIGABIT
338#define TSEC3_FLAGS TSEC_GIGABIT
339#define TSEC4_FLAGS TSEC_GIGABIT
340
341#define CONFIG_SYS_TBIPA_VALUE 0x1e
342
343#define CONFIG_ETHPRIME "eTSEC1"
344
345#endif
346
347
348
349
350
351#define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
352#define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP)
353#define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE )
354#define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U
355
356
357
358
359
360
361
362#define CONFIG_SYS_DBAT1L ( CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW \
363 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
364#define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_256M | BATU_VS | BATU_VP)
365#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
366#define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
367
368
369
370
371
372#define CONFIG_SYS_DBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW \
373 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
374#define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP)
375#define CONFIG_SYS_IBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
376#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
377
378
379
380
381
382#define CONFIG_SYS_DBAT3L ( CONFIG_SYS_CCSRBAR | BATL_PP_RW \
383 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
384#define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP)
385#define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
386#define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
387
388#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
389#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
390 | BATL_PP_RW | BATL_CACHEINHIBIT \
391 | BATL_GUARDEDSTORAGE)
392#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
393 | BATU_BL_1M | BATU_VS | BATU_VP)
394#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
395 | BATL_PP_RW | BATL_CACHEINHIBIT)
396#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
397#endif
398
399
400
401
402
403
404
405#define CONFIG_SYS_DBAT4L ( CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW \
406 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
407#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_32M | BATU_VS | BATU_VP)
408#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
409#define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
410
411
412
413
414
415#define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
416#define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
417#define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L
418#define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
419
420
421
422
423
424#define CONFIG_SYS_DBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW \
425 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
426#define CONFIG_SYS_DBAT6U ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP)
427#define CONFIG_SYS_IBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE)
428#define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
429
430
431#define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
432 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
433#define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
434#define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
435 | BATL_MEMCOHERENCE)
436#define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
437
438#define CONFIG_SYS_DBAT7L 0x00000000
439#define CONFIG_SYS_DBAT7U 0x00000000
440#define CONFIG_SYS_IBAT7L 0x00000000
441#define CONFIG_SYS_IBAT7U 0x00000000
442
443
444
445
446#define CONFIG_ENV_IS_IN_FLASH 1
447#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
448#define CONFIG_ENV_SECT_SIZE 0x20000
449#define CONFIG_ENV_SIZE 0x2000
450
451#define CONFIG_LOADS_ECHO 1
452#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
453
454#define CONFIG_CMD_REGINFO
455
456#if defined(CONFIG_PCI)
457 #define CONFIG_CMD_PCI
458#endif
459
460#undef CONFIG_WATCHDOG
461
462
463
464
465#define CONFIG_SYS_LONGHELP
466#define CONFIG_SYS_LOAD_ADDR 0x2000000
467#define CONFIG_CMDLINE_EDITING 1
468
469#if defined(CONFIG_CMD_KGDB)
470 #define CONFIG_SYS_CBSIZE 1024
471#else
472 #define CONFIG_SYS_CBSIZE 256
473#endif
474
475#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
476#define CONFIG_SYS_MAXARGS 16
477#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
478
479
480
481
482
483
484#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
485
486
487#define CONFIG_SYS_DCACHE_SIZE 32768
488#define CONFIG_SYS_CACHELINE_SIZE 32
489#if defined(CONFIG_CMD_KGDB)
490#define CONFIG_SYS_CACHELINE_SHIFT 5
491#endif
492
493#if defined(CONFIG_CMD_KGDB)
494#define CONFIG_KGDB_BAUDRATE 230400
495#endif
496
497
498
499
500
501#define CONFIG_HAS_ETH0 1
502#define CONFIG_HAS_ETH1 1
503#define CONFIG_HAS_ETH2 1
504#define CONFIG_HAS_ETH3 1
505
506#define CONFIG_IPADDR 192.168.0.50
507
508#define CONFIG_HOSTNAME sbc8641d
509#define CONFIG_ROOTPATH "/opt/eldk/ppc_74xx"
510#define CONFIG_BOOTFILE "uImage"
511
512#define CONFIG_SERVERIP 192.168.0.2
513#define CONFIG_GATEWAYIP 192.168.0.1
514#define CONFIG_NETMASK 255.255.255.0
515
516
517#define CONFIG_LOADADDR 1000000
518
519#undef CONFIG_BOOTARGS
520
521#define CONFIG_EXTRA_ENV_SETTINGS \
522 "netdev=eth0\0" \
523 "consoledev=ttyS0\0" \
524 "ramdiskaddr=2000000\0" \
525 "ramdiskfile=uRamdisk\0" \
526 "dtbaddr=400000\0" \
527 "dtbfile=sbc8641d.dtb\0" \
528 "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
529 "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
530 "maxcpus=1"
531
532#define CONFIG_NFSBOOTCOMMAND \
533 "setenv bootargs root=/dev/nfs rw " \
534 "nfsroot=$serverip:$rootpath " \
535 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
536 "console=$consoledev,$baudrate $othbootargs;" \
537 "tftp $loadaddr $bootfile;" \
538 "tftp $dtbaddr $dtbfile;" \
539 "bootm $loadaddr - $dtbaddr"
540
541#define CONFIG_RAMBOOTCOMMAND \
542 "setenv bootargs root=/dev/ram rw " \
543 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
544 "console=$consoledev,$baudrate $othbootargs;" \
545 "tftp $ramdiskaddr $ramdiskfile;" \
546 "tftp $loadaddr $bootfile;" \
547 "tftp $dtbaddr $dtbfile;" \
548 "bootm $loadaddr $ramdiskaddr $dtbaddr"
549
550#define CONFIG_FLASHBOOTCOMMAND \
551 "setenv bootargs root=/dev/ram rw " \
552 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
553 "console=$consoledev,$baudrate $othbootargs;" \
554 "bootm ffd00000 ffb00000 ffa00000"
555
556#define CONFIG_BOOTCOMMAND CONFIG_FLASHBOOTCOMMAND
557
558#endif
559