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15#ifndef __CONFIG_H
16#define __CONFIG_H
17
18
19
20
21
22#ifndef CONFIG_RAINIER
23#define CONFIG_440EPX 1
24#define CONFIG_HOSTNAME sequoia
25#else
26#define CONFIG_440GRX 1
27#define CONFIG_HOSTNAME rainier
28#endif
29#define CONFIG_440 1
30
31#ifndef CONFIG_SYS_TEXT_BASE
32#define CONFIG_SYS_TEXT_BASE 0xFFF80000
33#endif
34
35
36
37
38#include "amcc-common.h"
39
40
41#define CONFIG_SYS_CLK_FREQ ((in8(CONFIG_SYS_BCSR_BASE + 3) & 0x80) ? \
42 33333333 : 33000000)
43
44
45
46
47
48
49#ifdef CONFIG_VIDEO
50
51
52
53
54#define CONFIG_4xx_DCACHE
55#endif
56
57#define CONFIG_MISC_INIT_R 1
58
59
60
61
62
63#define CONFIG_SYS_TLB_FOR_BOOT_FLASH 0x0003
64#define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000
65#define CONFIG_SYS_FLASH_BASE 0xfc000000
66#define CONFIG_SYS_NAND_ADDR 0xd0000000
67#define CONFIG_SYS_OCM_BASE 0xe0010000
68#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_OCM_BASE
69#define CONFIG_SYS_PCI_BASE 0xe0000000
70#define CONFIG_SYS_PCI_MEMBASE 0x80000000
71#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000
72#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
73#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
74
75#define CONFIG_SYS_USB2D0_BASE 0xe0000100
76#define CONFIG_SYS_USB_DEVICE 0xe0000000
77#define CONFIG_SYS_USB_HOST 0xe0000400
78#define CONFIG_SYS_BCSR_BASE 0xc0000000
79
80
81
82
83
84#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE
85#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
86#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
87#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
88
89
90
91
92#define CONFIG_CONS_INDEX 1
93#define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200
94
95
96
97
98#if defined(CONFIG_SYS_RAMBOOT)
99#define CONFIG_ENV_IS_NOWHERE
100#define CONFIG_ENV_SIZE (8 << 10)
101#else
102#define CONFIG_ENV_IS_IN_FLASH
103#endif
104
105#if defined(CONFIG_CMD_FLASH)
106
107
108
109#define CONFIG_SYS_FLASH_CFI
110#define CONFIG_FLASH_CFI_DRIVER
111
112#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
113
114#define CONFIG_SYS_MAX_FLASH_BANKS 1
115#define CONFIG_SYS_MAX_FLASH_SECT 512
116
117#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
118#define CONFIG_SYS_FLASH_WRITE_TOUT 500
119
120#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
121#define CONFIG_SYS_FLASH_PROTECTION 1
122
123#define CONFIG_SYS_FLASH_EMPTY_INFO
124#define CONFIG_SYS_FLASH_QUIET_TEST 1
125#endif
126
127#ifdef CONFIG_ENV_IS_IN_FLASH
128#define CONFIG_ENV_SECT_SIZE 0x20000
129#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
130#define CONFIG_ENV_SIZE 0x2000
131
132
133#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
134#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
135#endif
136
137
138
139
140#define CONFIG_SYS_MBYTES_SDRAM (256)
141#if !defined(CONFIG_SYS_RAMBOOT)
142#define CONFIG_DDR_DATA_EYE
143#endif
144#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10)
145
146
147
148
149
150#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
151
152#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
153#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
154#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
155#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
156
157
158#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x52
159#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0
160#define CONFIG_4xx_CONFIG_BLOCKSIZE 16
161
162
163#define CONFIG_DTT_LM75 1
164#define CONFIG_DTT_AD7414 1
165#define CONFIG_DTT_SENSORS {0}
166#define CONFIG_SYS_DTT_MAX_TEMP 70
167#define CONFIG_SYS_DTT_LOW_TEMP -30
168#define CONFIG_SYS_DTT_HYSTERESIS 3
169
170
171
172
173#define CONFIG_EXTRA_ENV_SETTINGS \
174 CONFIG_AMCC_DEF_ENV \
175 CONFIG_AMCC_DEF_ENV_POWERPC \
176 CONFIG_AMCC_DEF_ENV_PPC_OLD \
177 CONFIG_AMCC_DEF_ENV_NOR_UPD \
178 "kernel_addr=FC000000\0" \
179 "ramdisk_addr=FC180000\0" \
180 ""
181
182#define CONFIG_M88E1111_PHY 1
183#define CONFIG_IBM_EMAC4_V4 1
184#define CONFIG_PHY_ADDR 0
185
186#define CONFIG_PHY_RESET 1
187#define CONFIG_PHY_GIGE 1
188
189#define CONFIG_HAS_ETH0
190#define CONFIG_HAS_ETH1 1
191#define CONFIG_PHY1_ADDR 1
192
193
194#ifdef CONFIG_440EPX
195
196#undef CONFIG_USB_EHCI
197
198#ifdef CONFIG_USB_EHCI
199#define CONFIG_USB_EHCI_PPC4XX
200#define CONFIG_SYS_PPC4XX_USB_ADDR 0xe0000300
201#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
202#define CONFIG_EHCI_MMIO_BIG_ENDIAN
203#define CONFIG_EHCI_DESC_BIG_ENDIAN
204#else
205#define CONFIG_USB_OHCI_NEW
206#define CONFIG_SYS_OHCI_BE_CONTROLLER
207
208#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
209#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
210#define CONFIG_SYS_USB_OHCI_REGS_BASE CONFIG_SYS_USB_HOST
211#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ppc440"
212#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
213#endif
214
215
216#define USB_2_0_DEVICE
217
218#endif
219
220
221
222
223
224
225#define CONFIG_CMD_DTT
226#define CONFIG_CMD_NAND
227#define CONFIG_CMD_PCI
228#define CONFIG_CMD_SDRAM
229
230#ifdef CONFIG_440EPX
231#endif
232
233#ifndef CONFIG_RAINIER
234#define CONFIG_SYS_POST_FPU_ON CONFIG_SYS_POST_FPU
235#else
236#define CONFIG_SYS_POST_FPU_ON 0
237#endif
238
239
240
241
242
243
244#if defined(CONFIG_SYS_RAMBOOT)
245#define CONFIG_SYS_POST_MEMORY_ON 0
246#else
247#define CONFIG_SYS_POST_MEMORY_ON CONFIG_SYS_POST_MEMORY
248#endif
249
250
251#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
252 CONFIG_SYS_POST_CPU | \
253 CONFIG_SYS_POST_ETHER | \
254 CONFIG_SYS_POST_FPU_ON | \
255 CONFIG_SYS_POST_I2C | \
256 CONFIG_SYS_POST_MEMORY_ON | \
257 CONFIG_SYS_POST_SPR | \
258 CONFIG_SYS_POST_UART)
259
260#define CONFIG_LOGBUFFER
261#define CONFIG_SYS_POST_CACHE_ADDR 0x7fff0000
262
263#define CONFIG_SUPPORT_VFAT
264
265
266
267
268
269#define CONFIG_PCI_INDIRECT_BRIDGE
270#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 0
271#define CONFIG_PCI_SCAN_SHOW
272#define CONFIG_SYS_PCI_TARGBASE 0x80000000
273
274
275#define CONFIG_SYS_PCI_TARGET_INIT
276#define CONFIG_SYS_PCI_MASTER_INIT
277#define CONFIG_SYS_PCI_BOARD_FIXUP_IRQ
278
279#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8
280#define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe
281
282
283
284
285
286
287
288
289#if !defined(CONFIG_SYS_RAMBOOT)
290#define CONFIG_SYS_NAND_CS 3
291
292#define CONFIG_SYS_EBC_PB0AP 0x03017200
293#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH_BASE | 0xda000)
294
295
296#define CONFIG_SYS_EBC_PB3AP 0x018003c0
297#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_NAND_ADDR | 0x1c000)
298#else
299#define CONFIG_SYS_NAND_CS 0
300
301#define CONFIG_SYS_EBC_PB3AP 0x03017200
302#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_FLASH_BASE | 0xda000)
303
304
305#define CONFIG_SYS_EBC_PB0AP 0x018003c0
306#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_NAND_ADDR | 0x1c000)
307#endif
308
309
310#define CONFIG_SYS_EBC_PB2AP 0x24814580
311#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_BCSR_BASE | 0x38000)
312
313#define CONFIG_SYS_BCSR5_PCI66EN 0x80
314
315
316
317
318#define CONFIG_SYS_MAX_NAND_DEVICE 1
319#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
320#define CONFIG_SYS_NAND_SELECT_DEVICE 1
321
322
323
324
325
326#define CONFIG_SYS_4xx_GPIO_TABLE { \
327{ \
328 \
329{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, \
330{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, \
331{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
332{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
333{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
334{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
335{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
336{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, \
337{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, \
338{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, \
339{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, \
340{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
341{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
342{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
343{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
344{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
345{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, \
346{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, \
347{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, \
348{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, \
349{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
350{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
351{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
352{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
353{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, \
354{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, \
355{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
356{GPIO0_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, \
357{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, \
358{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, \
359{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, \
360{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, \
361}, \
362{ \
363 \
364{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, \
365{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, \
366{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, \
367{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, \
368{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
369{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, \
370{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, \
371{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, \
372{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
373{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
374{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
375{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
376{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
377{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, \
378{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
379{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
380{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
381{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
382{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
383{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
384{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
385{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
386{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
387{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
388{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
389{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
390{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
391{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
392{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
393{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
394{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
395{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, \
396} \
397}
398
399#ifdef CONFIG_VIDEO
400#define CONFIG_BIOSEMU
401#define CONFIG_ATI_RADEON_FB
402#define VIDEO_IO_OFFSET 0xe8000000
403#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
404#define CONFIG_VIDEO_LOGO
405#define CONFIG_SPLASH_SCREEN
406#endif
407
408#endif
409