1/* 2 * Configuation settings for the Renesas Technology R0P7785LC0011RL board 3 * 4 * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9#ifndef __SH7785LCR_H 10#define __SH7785LCR_H 11 12#define CONFIG_CPU_SH7785 1 13#define CONFIG_SH7785LCR 1 14 15#define CONFIG_CMD_PCI 16#define CONFIG_CMD_SDRAM 17#define CONFIG_CMD_SH_ZIMAGEBOOT 18 19#define CONFIG_BOOTARGS "console=ttySC1,115200 root=/dev/nfs ip=dhcp" 20 21#define CONFIG_EXTRA_ENV_SETTINGS \ 22 "bootdevice=0:1\0" \ 23 "usbload=usb reset;usbboot;usb stop;bootm\0" 24 25#define CONFIG_DISPLAY_BOARDINFO 26#undef CONFIG_SHOW_BOOT_PROGRESS 27 28/* MEMORY */ 29#if defined(CONFIG_SH_32BIT) 30#define CONFIG_SYS_TEXT_BASE 0x8FF80000 31/* 0x40000000 - 0x47FFFFFF does not use */ 32#define CONFIG_SH_SDRAM_OFFSET (0x8000000) 33#define SH7785LCR_SDRAM_PHYS_BASE (0x40000000 + CONFIG_SH_SDRAM_OFFSET) 34#define SH7785LCR_SDRAM_BASE (0x80000000 + CONFIG_SH_SDRAM_OFFSET) 35#define SH7785LCR_SDRAM_SIZE (384 * 1024 * 1024) 36#define SH7785LCR_FLASH_BASE_1 (0xa0000000) 37#define SH7785LCR_FLASH_BANK_SIZE (64 * 1024 * 1024) 38#define SH7785LCR_USB_BASE (0xa6000000) 39#else 40#define CONFIG_SYS_TEXT_BASE 0x0FF80000 41#define SH7785LCR_SDRAM_BASE (0x08000000) 42#define SH7785LCR_SDRAM_SIZE (128 * 1024 * 1024) 43#define SH7785LCR_FLASH_BASE_1 (0xa0000000) 44#define SH7785LCR_FLASH_BANK_SIZE (64 * 1024 * 1024) 45#define SH7785LCR_USB_BASE (0xb4000000) 46#endif 47 48#define CONFIG_SYS_LONGHELP 49#define CONFIG_SYS_CBSIZE 256 50#define CONFIG_SYS_PBSIZE 256 51#define CONFIG_SYS_MAXARGS 16 52#define CONFIG_SYS_BARGSIZE 512 53#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } 54 55/* SCIF */ 56#define CONFIG_SCIF_CONSOLE 1 57#define CONFIG_CONS_SCIF1 1 58#define CONFIG_SCIF_EXT_CLOCK 1 59 60#define CONFIG_SYS_MEMTEST_START (SH7785LCR_SDRAM_BASE) 61#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ 62 (SH7785LCR_SDRAM_SIZE) - \ 63 4 * 1024 * 1024) 64#undef CONFIG_SYS_ALT_MEMTEST 65#undef CONFIG_SYS_MEMTEST_SCRATCH 66#undef CONFIG_SYS_LOADS_BAUD_CHANGE 67 68#define CONFIG_SYS_SDRAM_BASE (SH7785LCR_SDRAM_BASE) 69#define CONFIG_SYS_SDRAM_SIZE (SH7785LCR_SDRAM_SIZE) 70#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024) 71 72#define CONFIG_SYS_MONITOR_BASE (SH7785LCR_FLASH_BASE_1) 73#define CONFIG_SYS_MONITOR_LEN (512 * 1024) 74#define CONFIG_SYS_MALLOC_LEN (512 * 1024) 75#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 76 77/* FLASH */ 78#define CONFIG_FLASH_CFI_DRIVER 79#define CONFIG_SYS_FLASH_CFI 80#undef CONFIG_SYS_FLASH_QUIET_TEST 81#define CONFIG_SYS_FLASH_EMPTY_INFO 82#define CONFIG_SYS_FLASH_BASE (SH7785LCR_FLASH_BASE_1) 83#define CONFIG_SYS_MAX_FLASH_SECT 512 84 85#define CONFIG_SYS_MAX_FLASH_BANKS 1 86#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE + \ 87 (0 * SH7785LCR_FLASH_BANK_SIZE) } 88 89#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) 90#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) 91#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) 92#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) 93 94#undef CONFIG_SYS_FLASH_PROTECTION 95#undef CONFIG_SYS_DIRECT_FLASH_TFTP 96 97/* R8A66597 */ 98#define CONFIG_USB_R8A66597_HCD 99#define CONFIG_R8A66597_BASE_ADDR SH7785LCR_USB_BASE 100#define CONFIG_R8A66597_XTAL 0x0000 /* 12MHz */ 101#define CONFIG_R8A66597_LDRV 0x8000 /* 3.3V */ 102#define CONFIG_R8A66597_ENDIAN 0x0000 /* little */ 103 104/* PCI Controller */ 105#define CONFIG_SH4_PCI 106#define CONFIG_SH7780_PCI 107#if defined(CONFIG_SH_32BIT) 108#define CONFIG_SH7780_PCI_LSR 0x1ff00001 109#define CONFIG_SH7780_PCI_LAR 0x5f000000 110#define CONFIG_SH7780_PCI_BAR 0x5f000000 111#else 112#define CONFIG_SH7780_PCI_LSR 0x07f00001 113#define CONFIG_SH7780_PCI_LAR CONFIG_SYS_SDRAM_SIZE 114#define CONFIG_SH7780_PCI_BAR CONFIG_SYS_SDRAM_SIZE 115#endif 116#define CONFIG_PCI_SCAN_SHOW 1 117 118#define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */ 119#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS 120#define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */ 121 122#define CONFIG_PCI_IO_BUS 0xFE200000 /* IO space base address */ 123#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS 124#define CONFIG_PCI_IO_SIZE 0x00200000 /* Size of IO window */ 125 126#if defined(CONFIG_SH_32BIT) 127#define CONFIG_PCI_SYS_PHYS SH7785LCR_SDRAM_PHYS_BASE 128#else 129#define CONFIG_PCI_SYS_PHYS CONFIG_SYS_SDRAM_BASE 130#endif 131#define CONFIG_PCI_SYS_BUS CONFIG_SYS_SDRAM_BASE 132#define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE 133 134/* ENV setting */ 135#define CONFIG_ENV_IS_IN_FLASH 136#define CONFIG_ENV_OVERWRITE 1 137#define CONFIG_ENV_SECT_SIZE (256 * 1024) 138#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) 139#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) 140#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) 141#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) 142 143/* Board Clock */ 144/* The SCIF used external clock. system clock only used timer. */ 145#define CONFIG_SYS_CLK_FREQ 50000000 146#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ 147#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 148#define CONFIG_SYS_TMU_CLK_DIV 4 149 150#endif /* __SH7785LCR_H */ 151