LXR uboot/include/configs/suvd3.h

   1/*
   2 * Copyright (C) 2006 Freescale Semiconductor, Inc.
   3 *                    Dave Liu <daveliu@freescale.com>
   4 *
   5 * Copyright (C) 2007 Logic Product Development, Inc.
   6 *                    Peter Barada <peterb@logicpd.com>
   7 *
   8 * Copyright (C) 2007 MontaVista Software, Inc.
   9 *                    Anton Vorontsov <avorontsov@ru.mvista.com>
  10 *
  11 * (C) Copyright 2010
  12 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  13 *
  14 * SPDX-License-Identifier:     GPL-2.0+
  15 */
  16
  17#ifndef __CONFIG_H
  18#define __CONFIG_H
  19
  20/*
  21 * High Level Configuration Options
  22 */
  23
  24/* This needs to be set prior to including km/km83xx-common.h */
  25#define CONFIG_SYS_TEXT_BASE    0xF0000000
  26
  27#if defined(CONFIG_SUVD3)       /* SUVD3 board specific */
  28#define CONFIG_HOSTNAME         suvd3
  29#define CONFIG_KM_BOARD_NAME   "suvd3"
  30/* include common defines/options for all 8321 Keymile boards */
  31#include "km/km8321-common.h"
  32
  33#elif defined(CONFIG_KMVECT1)   /* VECT1 board specific */
  34#define CONFIG_HOSTNAME         kmvect1
  35#define CONFIG_KM_BOARD_NAME   "kmvect1"
  36/* at end of uboot partition, before env */
  37#define CONFIG_SYS_QE_FW_ADDR   0xF00B0000
  38/* include common defines/options for all 8309 Keymile boards */
  39#include "km/km8309-common.h"
  40
  41#elif defined(CONFIG_KMTEGR1)   /* TEGR1 board specific */
  42#define CONFIG_HOSTNAME   kmtegr1
  43#define CONFIG_KM_BOARD_NAME   "kmtegr1"
  44#define CONFIG_KM_UBI_PARTITION_NAME_BOOT       "ubi0"
  45#define CONFIG_KM_UBI_PARTITION_NAME_APP        "ubi1"
  46#define MTDIDS_DEFAULT                  "nor0=boot,nand0=app"
  47#define MTDPARTS_DEFAULT                "mtdparts="                     \
  48        "boot:"                                                         \
  49                "768k(u-boot),"                                         \
  50                "256k(qe-fw),"                                          \
  51                "128k(env),"                                            \
  52                "128k(envred),"                                         \
  53                "-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ");"             \
  54        "app:"                                                          \
  55                "-(" CONFIG_KM_UBI_PARTITION_NAME_APP ");"
  56
  57#define CONFIG_ENV_ADDR         0xF0100000
  58#define CONFIG_ENV_OFFSET       0x100000
  59
  60#define CONFIG_CMD_NAND
  61#define CONFIG_NAND_ECC_BCH
  62#define CONFIG_BCH
  63#define CONFIG_NAND_KMETER1
  64#define CONFIG_SYS_MAX_NAND_DEVICE              1
  65#define NAND_MAX_CHIPS                          1
  66
  67/* include common defines/options for all 8309 Keymile boards */
  68#include "km/km8309-common.h"
  69/* must be after the include because KMBEC_FPGA is otherwise undefined */
  70#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */
  71
  72#else
  73#error Supported boards are: SUVD3, KMVECT1, KMTEGR1
  74#endif
  75
  76#define CONFIG_SYS_APP1_BASE            0xA0000000
  77#define CONFIG_SYS_APP1_SIZE            256 /* Megabytes */
  78#define CONFIG_SYS_APP2_BASE            0xB0000000
  79#define CONFIG_SYS_APP2_SIZE            256 /* Megabytes */
  80
  81/* EEprom support */
  82#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
  83
  84/*
  85 * Init Local Bus Memory Controller:
  86 *
  87 * Bank Bus     Machine PortSz  Size  Device
  88 * ---- ---     ------- ------  -----  ------
  89 *  2   Local   UPMA    16 bit  256MB APP1
  90 *  3   Local   GPCM    16 bit  256MB APP2
  91 *
  92 */
  93
  94#if defined(CONFIG_SUVD3) || defined(CONFIG_KMVECT1)
  95/*
  96 * APP1 on the local bus CS2
  97 */
  98#define CONFIG_SYS_LBLAWBAR2_PRELIM     CONFIG_SYS_APP1_BASE
  99#define CONFIG_SYS_LBLAWAR2_PRELIM      (LBLAWAR_EN | LBLAWAR_256MB)
 100
 101#define CONFIG_SYS_BR2_PRELIM   (CONFIG_SYS_APP1_BASE | \
 102                                 BR_PS_16 | \
 103                                 BR_MS_UPMA | \
 104                                 BR_V)
 105#define CONFIG_SYS_OR2_PRELIM   (MEG_TO_AM(CONFIG_SYS_APP1_SIZE))
 106
 107#define CONFIG_SYS_BR3_PRELIM   (CONFIG_SYS_APP2_BASE | \
 108                                 BR_PS_16 | \
 109                                 BR_V)
 110
 111#define CONFIG_SYS_OR3_PRELIM   (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \
 112                                 OR_GPCM_CSNT | \
 113                                 OR_GPCM_ACS_DIV4 | \
 114                                 OR_GPCM_SCY_3 | \
 115                                 OR_GPCM_TRLX_SET)
 116
 117#define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \
 118                         0x0000c000 | \
 119                         MxMR_WLFx_2X)
 120
 121#elif defined(CONFIG_KMTEGR1)
 122#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \
 123                                 BR_PS_16 | \
 124                                 BR_MS_GPCM | \
 125                                 BR_V)
 126
 127#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \
 128                                 OR_GPCM_SCY_5 | \
 129                                 OR_GPCM_TRLX_CLEAR | \
 130                                 OR_GPCM_EHTR_CLEAR)
 131
 132#endif /* CONFIG_KMTEGR1 */
 133
 134#define CONFIG_SYS_LBLAWBAR3_PRELIM     CONFIG_SYS_APP2_BASE
 135#define CONFIG_SYS_LBLAWAR3_PRELIM      (LBLAWAR_EN | LBLAWAR_256MB)
 136
 137/*
 138 * MMU Setup
 139 */
 140#if defined(CONFIG_SUVD3) || defined(CONFIG_KMVECT1)
 141/* APP1:  icache cacheable, but dcache-inhibit and guarded */
 142#define CONFIG_SYS_IBAT5L       (CONFIG_SYS_APP1_BASE | BATL_PP_RW | \
 143                                 BATL_MEMCOHERENCE)
 144#define CONFIG_SYS_IBAT5U       (CONFIG_SYS_APP1_BASE | BATU_BL_256M | \
 145                                 BATU_VS | BATU_VP)
 146#define CONFIG_SYS_DBAT5L       (CONFIG_SYS_APP1_BASE | BATL_PP_RW | \
 147                                 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 148#define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 149
 150#elif defined(CONFIG_KMTEGR1)
 151#define CONFIG_SYS_IBAT5L (0)
 152#define CONFIG_SYS_IBAT5U (0)
 153#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
 154#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
 155#endif /* CONFIG_KMTEGR1 */
 156
 157#define CONFIG_SYS_IBAT6L       (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \
 158                                 BATL_MEMCOHERENCE)
 159#define CONFIG_SYS_IBAT6U       (CONFIG_SYS_APP2_BASE | BATU_BL_256M | \
 160                                 BATU_VS | BATU_VP)
 161#define CONFIG_SYS_DBAT6L       (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \
 162                                 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 163#define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 164
 165/*
 166 * QE UEC ethernet configuration
 167 */
 168#if defined(CONFIG_KMVECT1)
 169#define CONFIG_MV88E6352_SWITCH
 170#define CONFIG_KM_MVEXTSW_ADDR          0x10
 171
 172/* ethernet port connected to simple switch 88e6122 (UEC0) */
 173#define CONFIG_UEC_ETH1
 174#define CONFIG_SYS_UEC1_UCC_NUM         0       /* UCC1 */
 175#define CONFIG_SYS_UEC1_RX_CLK          QE_CLK9
 176#define CONFIG_SYS_UEC1_TX_CLK          QE_CLK10
 177
 178#define CONFIG_FIXED_PHY                0xFFFFFFFF
 179#define CONFIG_SYS_FIXED_PHY_ADDR       0x1E    /* unused address */
 180#define CONFIG_SYS_FIXED_PHY_PORT(devnum, speed, duplex) \
 181                {devnum, speed, duplex}
 182#define CONFIG_SYS_FIXED_PHY_PORTS \
 183                CONFIG_SYS_FIXED_PHY_PORT("UEC0", SPEED_100, DUPLEX_FULL)
 184
 185#define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
 186#define CONFIG_SYS_UEC1_PHY_ADDR        CONFIG_SYS_FIXED_PHY_ADDR
 187#define CONFIG_SYS_UEC1_INTERFACE_TYPE  PHY_INTERFACE_MODE_MII
 188#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
 189#endif /* CONFIG_KMVECT1 */
 190
 191#if defined(CONFIG_KMVECT1) || defined(CONFIG_KMTEGR1)
 192/* ethernet port connected to piggy (UEC2) */
 193#define CONFIG_HAS_ETH1
 194#define CONFIG_UEC_ETH2
 195#define CONFIG_SYS_UEC2_UCC_NUM         2       /* UCC3 */
 196#define CONFIG_SYS_UEC2_RX_CLK          QE_CLK_NONE /* not used in RMII Mode */
 197#define CONFIG_SYS_UEC2_TX_CLK          QE_CLK12
 198#define CONFIG_SYS_UEC2_ETH_TYPE        FAST_ETH
 199#define CONFIG_SYS_UEC2_PHY_ADDR        0
 200#define CONFIG_SYS_UEC2_INTERFACE_TYPE  PHY_INTERFACE_MODE_RMII
 201#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
 202#endif /* CONFIG_KMVECT1 || CONFIG_KMTEGR1 */
 203
 204#endif /* __CONFIG_H */
 205