1/* 2 * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7#ifndef _TEGRA114_COMMON_H_ 8#define _TEGRA114_COMMON_H_ 9#include "tegra-common.h" 10 11/* 12 * NS16550 Configuration 13 */ 14#define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */ 15 16/* 17 * Miscellaneous configurable options 18 */ 19#define CONFIG_STACKBASE 0x82800000 /* 40MB */ 20 21/*----------------------------------------------------------------------- 22 * Physical Memory Map 23 */ 24#define CONFIG_SYS_TEXT_BASE 0x80110000 25 26/* 27 * Memory layout for where various images get loaded by boot scripts: 28 * 29 * scriptaddr can be pretty much anywhere that doesn't conflict with something 30 * else. Put it above BOOTMAPSZ to eliminate conflicts. 31 * 32 * pxefile_addr_r can be pretty much anywhere that doesn't conflict with 33 * something else. Put it above BOOTMAPSZ to eliminate conflicts. 34 * 35 * kernel_addr_r must be within the first 128M of RAM in order for the 36 * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will 37 * decompress itself to 0x8000 after the start of RAM, kernel_addr_r 38 * should not overlap that area, or the kernel will have to copy itself 39 * somewhere else before decompression. Similarly, the address of any other 40 * data passed to the kernel shouldn't overlap the start of RAM. Pushing 41 * this up to 16M allows for a sizable kernel to be decompressed below the 42 * compressed load address. 43 * 44 * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for 45 * the compressed kernel to be up to 16M too. 46 * 47 * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows 48 * for the FDT/DTB to be up to 1M, which is hopefully plenty. 49 */ 50#define CONFIG_LOADADDR 0x81000000 51#define MEM_LAYOUT_ENV_SETTINGS \ 52 "scriptaddr=0x90000000\0" \ 53 "pxefile_addr_r=0x90100000\0" \ 54 "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ 55 "fdt_addr_r=0x82000000\0" \ 56 "ramdisk_addr_r=0x82100000\0" 57 58/* Defines for SPL */ 59#define CONFIG_SPL_TEXT_BASE 0x80108000 60#define CONFIG_SYS_SPL_MALLOC_START 0x80090000 61#define CONFIG_SPL_STACK 0x800ffffc 62 63/* For USB EHCI controller */ 64#define CONFIG_EHCI_IS_TDI 65#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10 66#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1 67 68#endif /* _TEGRA114_COMMON_H_ */ 69