1/* 2 * (C) Copyright 2013 3 * NVIDIA Corporation <www.nvidia.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8#ifndef _TEGRA124_COMMON_H_ 9#define _TEGRA124_COMMON_H_ 10 11#include "tegra-common.h" 12 13/* 14 * NS16550 Configuration 15 */ 16#define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */ 17 18/* 19 * Miscellaneous configurable options 20 */ 21#define CONFIG_STACKBASE 0x82800000 /* 40MB */ 22 23/*----------------------------------------------------------------------- 24 * Physical Memory Map 25 */ 26#define CONFIG_SYS_TEXT_BASE 0x80110000 27 28/* 29 * Memory layout for where various images get loaded by boot scripts: 30 * 31 * scriptaddr can be pretty much anywhere that doesn't conflict with something 32 * else. Put it above BOOTMAPSZ to eliminate conflicts. 33 * 34 * pxefile_addr_r can be pretty much anywhere that doesn't conflict with 35 * something else. Put it above BOOTMAPSZ to eliminate conflicts. 36 * 37 * kernel_addr_r must be within the first 128M of RAM in order for the 38 * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will 39 * decompress itself to 0x8000 after the start of RAM, kernel_addr_r 40 * should not overlap that area, or the kernel will have to copy itself 41 * somewhere else before decompression. Similarly, the address of any other 42 * data passed to the kernel shouldn't overlap the start of RAM. Pushing 43 * this up to 16M allows for a sizable kernel to be decompressed below the 44 * compressed load address. 45 * 46 * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for 47 * the compressed kernel to be up to 16M too. 48 * 49 * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows 50 * for the FDT/DTB to be up to 1M, which is hopefully plenty. 51 */ 52#define CONFIG_LOADADDR 0x81000000 53#define MEM_LAYOUT_ENV_SETTINGS \ 54 "scriptaddr=0x90000000\0" \ 55 "pxefile_addr_r=0x90100000\0" \ 56 "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ 57 "fdt_addr_r=0x82000000\0" \ 58 "ramdisk_addr_r=0x82100000\0" 59 60/* Defines for SPL */ 61#define CONFIG_SPL_TEXT_BASE 0x80108000 62#define CONFIG_SYS_SPL_MALLOC_START 0x80090000 63#define CONFIG_SPL_STACK 0x800ffffc 64 65/* For USB EHCI controller */ 66#define CONFIG_EHCI_IS_TDI 67#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10 68#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1 69 70/* GPU needs setup */ 71#define CONFIG_TEGRA_GPU 72 73#endif /* _TEGRA124_COMMON_H_ */ 74