LXR uboot/include/configs/tegra186-common.h

   1/*
   2 * Copyright 2013-2016, NVIDIA CORPORATION.
   3 *
   4 * SPDX-License-Identifier: GPL-2.0
   5 */
   6
   7#ifndef _TEGRA186_COMMON_H_
   8#define _TEGRA186_COMMON_H_
   9
  10#include "tegra-common.h"
  11
  12/*
  13 * NS16550 Configuration
  14 */
  15#define V_NS16550_CLK           408000000       /* 408MHz (pllp_out0) */
  16
  17/*
  18 * Miscellaneous configurable options
  19 */
  20#define CONFIG_STACKBASE        0x82800000      /* 40MB */
  21
  22/*-----------------------------------------------------------------------
  23 * Physical Memory Map
  24 */
  25
  26#define CONFIG_SYS_TEXT_BASE    0x80080000
  27
  28/* Generic Interrupt Controller */
  29#define CONFIG_GICV2
  30
  31/*
  32 * Memory layout for where various images get loaded by boot scripts:
  33 *
  34 * scriptaddr can be pretty much anywhere that doesn't conflict with something
  35 *   else. Put it above BOOTMAPSZ to eliminate conflicts.
  36 *
  37 * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
  38 *   something else. Put it above BOOTMAPSZ to eliminate conflicts.
  39 *
  40 * kernel_addr_r must be within the first 128M of RAM in order for the
  41 *   kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
  42 *   decompress itself to 0x8000 after the start of RAM, kernel_addr_r
  43 *   should not overlap that area, or the kernel will have to copy itself
  44 *   somewhere else before decompression. Similarly, the address of any other
  45 *   data passed to the kernel shouldn't overlap the start of RAM. Pushing
  46 *   this up to 16M allows for a sizable kernel to be decompressed below the
  47 *   compressed load address.
  48 *
  49 * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
  50 *   the compressed kernel to be up to 16M too.
  51 *
  52 * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
  53 *   for the FDT/DTB to be up to 1M, which is hopefully plenty.
  54 */
  55#define CONFIG_LOADADDR 0x80080000
  56#define MEM_LAYOUT_ENV_SETTINGS \
  57        "scriptaddr=0x90000000\0" \
  58        "pxefile_addr_r=0x90100000\0" \
  59        "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
  60        "fdt_addr_r=0x82000000\0" \
  61        "ramdisk_addr_r=0x82100000\0"
  62
  63/* Defines for SPL */
  64#define CONFIG_SPL_TEXT_BASE            0x80108000
  65#define CONFIG_SYS_SPL_MALLOC_START     0x80090000
  66#define CONFIG_SPL_STACK                0x800ffffc
  67
  68#endif
  69