1/* 2 * (C) Copyright 2010-2012 3 * NVIDIA Corporation <www.nvidia.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8#ifndef _TEGRA20_COMMON_H_ 9#define _TEGRA20_COMMON_H_ 10#include "tegra-common.h" 11 12/* 13 * NS16550 Configuration 14 */ 15#define V_NS16550_CLK 216000000 /* 216MHz (pllp_out0) */ 16 17/* 18 * Miscellaneous configurable options 19 */ 20#define CONFIG_STACKBASE 0x02800000 /* 40MB */ 21 22/*----------------------------------------------------------------------- 23 * Physical Memory Map 24 */ 25#define CONFIG_SYS_TEXT_BASE 0x00110000 26 27/* 28 * Memory layout for where various images get loaded by boot scripts: 29 * 30 * scriptaddr can be pretty much anywhere that doesn't conflict with something 31 * else. Put it above BOOTMAPSZ to eliminate conflicts. 32 * 33 * pxefile_addr_r can be pretty much anywhere that doesn't conflict with 34 * something else. Put it above BOOTMAPSZ to eliminate conflicts. 35 * 36 * kernel_addr_r must be within the first 128M of RAM in order for the 37 * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will 38 * decompress itself to 0x8000 after the start of RAM, kernel_addr_r 39 * should not overlap that area, or the kernel will have to copy itself 40 * somewhere else before decompression. Similarly, the address of any other 41 * data passed to the kernel shouldn't overlap the start of RAM. Pushing 42 * this up to 16M allows for a sizable kernel to be decompressed below the 43 * compressed load address. 44 * 45 * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for 46 * the compressed kernel to be up to 16M too. 47 * 48 * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows 49 * for the FDT/DTB to be up to 1M, which is hopefully plenty. 50 */ 51#define CONFIG_LOADADDR 0x01000000 52#define MEM_LAYOUT_ENV_SETTINGS \ 53 "scriptaddr=0x10000000\0" \ 54 "pxefile_addr_r=0x10100000\0" \ 55 "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ 56 "fdt_addr_r=0x02000000\0" \ 57 "ramdisk_addr_r=0x02100000\0" 58 59/* Defines for SPL */ 60#define CONFIG_SPL_TEXT_BASE 0x00108000 61#define CONFIG_SYS_SPL_MALLOC_START 0x00090000 62#define CONFIG_SPL_STACK 0x000ffffc 63 64/* Align LCD to 1MB boundary */ 65#define CONFIG_LCD_ALIGNMENT MMU_SECTION_SIZE 66 67#ifdef CONFIG_TEGRA_LP0 68#define TEGRA_LP0_ADDR 0x1C406000 69#define TEGRA_LP0_SIZE 0x2000 70#define TEGRA_LP0_VEC \ 71 "lp0_vec=" __stringify(TEGRA_LP0_SIZE) \ 72 "@" __stringify(TEGRA_LP0_ADDR) " " 73#else 74#define TEGRA_LP0_VEC 75#endif 76 77/* 78 * This parameter affects a TXFILLTUNING field that controls how much data is 79 * sent to the latency fifo before it is sent to the wire. Without this 80 * parameter, the default (2) causes occasional Data Buffer Errors in OUT 81 * packets depending on the buffer address and size. 82 */ 83#define CONFIG_USB_EHCI_TXFIFO_THRESH 10 84#define CONFIG_EHCI_IS_TDI 85#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1 86 87#define CONFIG_SYS_NAND_SELF_INIT 88#define CONFIG_SYS_NAND_ONFI_DETECTION 89 90#endif /* _TEGRA20_COMMON_H_ */ 91