1/* 2 * ti816x_evm.h 3 * 4 * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com> 5 * Antoine Tenart, <atenart@adeneo-embedded.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10#ifndef __CONFIG_TI816X_EVM_H 11#define __CONFIG_TI816X_EVM_H 12 13#define CONFIG_TI81XX 14#define CONFIG_TI816X 15#define CONFIG_OMAP 16 17#define CONFIG_ARCH_CPU_INIT 18 19#include <asm/arch/omap.h> 20 21#define CONFIG_ENV_SIZE 0x2000 22#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (32 * 1024)) 23#define CONFIG_SYS_LONGHELP /* undef save memory */ 24#define CONFIG_MACH_TYPE MACH_TYPE_TI8168EVM 25 26#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 27#define CONFIG_SETUP_MEMORY_TAGS 28#define CONFIG_INITRD_TAG /* required for ramdisk support */ 29 30#define CONFIG_EXTRA_ENV_SETTINGS \ 31 "loadaddr=0x81000000\0" \ 32 33#define CONFIG_BOOTCOMMAND \ 34 "mmc rescan;" \ 35 "fatload mmc 0 ${loadaddr} uImage;" \ 36 "bootm ${loadaddr}" \ 37 38#define CONFIG_BOOTARGS "console=ttyO2,115200n8 noinitrd earlyprintk" 39 40/* Clock Defines */ 41#define V_OSCK 24000000 /* Clock output from T2 */ 42#define V_SCLK (V_OSCK >> 1) 43 44#define CONFIG_SYS_MAXARGS 32 45#define CONFIG_SYS_CBSIZE 512 /* console I/O buffer size */ 46#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ 47 + sizeof(CONFIG_SYS_PROMPT) + 16) /* print buffer size */ 48#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* boot arg buffer size */ 49 50#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default load address */ 51 52#define CONFIG_CMD_ASKENV 53#define CONFIG_OMAP_GPIO 54 55#define CONFIG_FS_FAT 56 57/* 58 * Only one of the following two options (DDR3/DDR2) should be enabled 59 * CONFIG_TI816X_EVM_DDR2 60 * CONFIG_TI816X_EVM_DDR3 61 */ 62#define CONFIG_TI816X_EVM_DDR3 63 64/* 65 * Supported values: 400, 531, 675 or 796 MHz 66 */ 67#define CONFIG_TI816X_DDR_PLL_796 68 69#define CONFIG_TI816X_USE_EMIF0 1 70#define CONFIG_TI816X_USE_EMIF1 1 71 72#define CONFIG_NR_DRAM_BANKS 2 /* we have 2 banks of DRAM */ 73#define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */ 74#define PHYS_DRAM_1_SIZE 0x40000000 /* 1 GB */ 75#define PHYS_DRAM_2 0xC0000000 /* DRAM Bank #2 */ 76#define PHYS_DRAM_2_SIZE 0x40000000 /* 1 GB */ 77 78#define CONFIG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2048MB */ 79#define CONFIG_SYS_SDRAM_BASE PHYS_DRAM_1 80#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ 81 GENERATED_GBL_DATA_SIZE) 82 83/** 84 * Platform/Board specific defs 85 */ 86#define CONFIG_SYS_CLK_FREQ 27000000 87#define CONFIG_SYS_TIMERBASE 0x4802E000 88#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 89 90#undef CONFIG_NAND_OMAP_GPMC 91 92/* 93 * NS16550 Configuration 94 */ 95#define CONFIG_SYS_NS16550_SERIAL 96#define CONFIG_SYS_NS16550_REG_SIZE (-4) 97#define CONFIG_SYS_NS16550_CLK (48000000) 98#define CONFIG_SYS_NS16550_COM1 0x48024000 /* Base EVM has UART2 */ 99 100/* allow overwriting serial config and ethaddr */ 101#define CONFIG_ENV_OVERWRITE 102 103#define CONFIG_SERIAL1 104#define CONFIG_SERIAL2 105#define CONFIG_SERIAL3 106#define CONFIG_CONS_INDEX 1 107 108#define CONFIG_ENV_IS_NOWHERE 109 110/* SPL */ 111/* Defines for SPL */ 112#define CONFIG_SPL_FRAMEWORK 113#define CONFIG_SPL_TEXT_BASE 0x40400000 114#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ 115 CONFIG_SPL_TEXT_BASE) 116 117#define CONFIG_SPL_BSS_START_ADDR 0x80000000 118#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 119 120#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 121#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 122 123#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 124#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000 125#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" 126 127#define CONFIG_SPL_BOARD_INIT 128 129#define CONFIG_SYS_TEXT_BASE 0x80800000 130#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 131#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 132 133/* Since SPL did pll and ddr initialization for us, 134 * we don't need to do it twice. 135 */ 136#ifndef CONFIG_SPL_BUILD 137#define CONFIG_SKIP_LOWLEVEL_INIT 138#endif 139 140#endif 141