1/* 2 * (C) Copyright 2003-2006 Wolfgang Denk, DENX Software Engineering, 3 * wd@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8#ifndef __CONFIG_H 9#define __CONFIG_H 10 11/* 12 * High Level Configuration Options 13 * (easy to change) 14 */ 15#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ 16#define CONFIG_V38B 1 /* ...on V38B board */ 17 18#define CONFIG_SYS_TEXT_BASE 0xFF000000 19 20#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ...running at 33.000000MHz */ 21 22#define CONFIG_RTC_PCF8563 1 /* has PCF8563 RTC */ 23#define CONFIG_MPC5200_DDR 1 /* has DDR SDRAM */ 24 25#undef CONFIG_HW_WATCHDOG /* don't use watchdog */ 26 27#define CONFIG_NETCONSOLE 1 28 29#define CONFIG_BOARD_EARLY_INIT_R 1 /* do board-specific init */ 30#define CONFIG_MISC_INIT_R 31 32#define CONFIG_SYS_XLB_PIPELINING 1 /* gives better performance */ 33 34#define CONFIG_HIGH_BATS 1 /* High BATs supported */ 35 36/* 37 * Serial console configuration 38 */ 39#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ 40#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } 41 42/* 43 * DDR 44 */ 45#define SDRAM_DDR 1 /* is DDR */ 46/* Settings for XLB = 132 MHz */ 47#define SDRAM_MODE 0x018D0000 48#define SDRAM_EMODE 0x40090000 49#define SDRAM_CONTROL 0x704f0f00 50#define SDRAM_CONFIG1 0x73722930 51#define SDRAM_CONFIG2 0x47770000 52#define SDRAM_TAPDELAY 0x10000000 53 54/* 55 * PCI - no support 56 */ 57 58/* 59 * USB 60 */ 61#define CONFIG_USB_OHCI 62#define CONFIG_USB_CLOCK 0x0001BBBB 63#define CONFIG_USB_CONFIG 0x00001000 64 65/* 66 * BOOTP options 67 */ 68#define CONFIG_BOOTP_BOOTFILESIZE 69#define CONFIG_BOOTP_BOOTPATH 70#define CONFIG_BOOTP_GATEWAY 71#define CONFIG_BOOTP_HOSTNAME 72 73/* 74 * Command line configuration. 75 */ 76#define CONFIG_CMD_IDE 77#define CONFIG_CMD_IRQ 78#define CONFIG_CMD_JFFS2 79#define CONFIG_CMD_SDRAM 80 81#define CONFIG_TIMESTAMP /* Print image info with timestamp */ 82 83/* 84 * Boot low with 16 MB Flash 85 */ 86#define CONFIG_SYS_LOWBOOT 1 87#define CONFIG_SYS_LOWBOOT16 1 88 89/* 90 * Autobooting 91 */ 92 93#define CONFIG_PREBOOT "echo;" \ 94 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ 95 "echo" 96 97#undef CONFIG_BOOTARGS 98 99#define CONFIG_EXTRA_ENV_SETTINGS \ 100 "bootcmd=run net_nfs\0" \ 101 "bootdelay=3\0" \ 102 "baudrate=115200\0" \ 103 "preboot=echo;echo Type \"run flash_nfs\" to mount root " \ 104 "filesystem over NFS; echo\0" \ 105 "netdev=eth0\0" \ 106 "ramargs=setenv bootargs root=/dev/ram rw wdt=off \0" \ 107 "addip=setenv bootargs $(bootargs) " \ 108 "ip=$(ipaddr):$(serverip):$(gatewayip):" \ 109 "$(netmask):$(hostname):$(netdev):off panic=1\0" \ 110 "flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0" \ 111 "flash_self=run ramargs addip;bootm $(kernel_addr) " \ 112 "$(ramdisk_addr)\0" \ 113 "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \ 114 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 115 "nfsroot=$(serverip):$(rootpath) wdt=off\0" \ 116 "hostname=v38b\0" \ 117 "ethact=FEC\0" \ 118 "rootpath=/opt/eldk-3.1.1/ppc_6xx\0" \ 119 "update=prot off ff000000 ff03ffff; era ff000000 ff03ffff; " \ 120 "cp.b 200000 ff000000 $(filesize);" \ 121 "prot on ff000000 ff03ffff\0" \ 122 "load=tftp 200000 $(u-boot)\0" \ 123 "netmask=255.255.0.0\0" \ 124 "ipaddr=192.168.160.18\0" \ 125 "serverip=192.168.1.1\0" \ 126 "bootfile=/tftpboot/v38b/uImage\0" \ 127 "u-boot=/tftpboot/v38b/u-boot.bin\0" \ 128 "" 129 130#define CONFIG_BOOTCOMMAND "run net_nfs" 131 132/* 133 * IPB Bus clocking configuration. 134 */ 135#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ 136 137/* 138 * I2C configuration 139 */ 140#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ 141#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */ 142#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ 143#define CONFIG_SYS_I2C_SLAVE 0x7F 144 145/* 146 * EEPROM configuration 147 */ 148#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ 149#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 150#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 151#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70 152 153/* 154 * RTC configuration 155 */ 156#define CONFIG_SYS_I2C_RTC_ADDR 0x51 157 158/* 159 * Flash configuration - use CFI driver 160 */ 161#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ 162#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ 163#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 164#define CONFIG_SYS_FLASH_BASE 0xFF000000 165#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ 166#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 167#define CONFIG_SYS_FLASH_SIZE 0x01000000 /* 16 MiB */ 168#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */ 169#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* flash write speed-up */ 170 171/* 172 * Environment settings 173 */ 174#define CONFIG_ENV_IS_IN_FLASH 1 175#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000) 176#define CONFIG_ENV_SIZE 0x10000 177#define CONFIG_ENV_SECT_SIZE 0x10000 178#define CONFIG_ENV_OVERWRITE 1 179 180/* 181 * Memory map 182 */ 183#define CONFIG_SYS_MBAR 0xF0000000 184#define CONFIG_SYS_SDRAM_BASE 0x00000000 185#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 186 187/* Use SRAM until RAM will be available */ 188#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM 189#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */ 190 191#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 192#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 193 194#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 195#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 196# define CONFIG_SYS_RAMBOOT 1 197#endif 198 199#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256kB for Monitor */ 200#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128kB for malloc() */ 201#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Linux initial memory map */ 202 203/* 204 * Ethernet configuration 205 */ 206#define CONFIG_MPC5xxx_FEC 1 207#define CONFIG_MPC5xxx_FEC_MII100 208#define CONFIG_PHY_ADDR 0x00 209#define CONFIG_MII 1 210 211/* 212 * GPIO configuration 213 */ 214#define CONFIG_SYS_GPS_PORT_CONFIG 0x90001404 215 216/* 217 * Miscellaneous configurable options 218 */ 219#define CONFIG_SYS_LONGHELP /* undef to save memory */ 220#if defined(CONFIG_CMD_KGDB) 221#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 222#else 223#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 224#endif 225#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 226#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 227#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 228 229#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ 230#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ 231 232#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 233 234#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ 235#if defined(CONFIG_CMD_KGDB) 236# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ 237#endif 238 239/* 240 * Various low-level settings 241 */ 242#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI 243#define CONFIG_SYS_HID0_FINAL HID0_ICE 244 245#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE 246#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE 247#define CONFIG_SYS_BOOTCS_CFG 0x00047801 248#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE 249#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE 250 251#define CONFIG_SYS_CS_BURST 0x00000000 252#define CONFIG_SYS_CS_DEADCYCLE 0x33333333 253 254#define CONFIG_SYS_RESET_ADDRESS 0xff000000 255 256/* 257 * IDE/ATA (supports IDE harddisk) 258 */ 259#undef CONFIG_IDE_8xx_PCCARD /* Don't use IDE with PC Card Adapter */ 260#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ 261#undef CONFIG_IDE_LED /* LED for ide not supported */ 262 263#define CONFIG_IDE_RESET /* reset for ide supported */ 264#define CONFIG_IDE_PREINIT 265 266#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ 267#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ 268 269#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 270 271#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA 272 273#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) /* data I/O offset */ 274 275#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) /* normal register accesses offset */ 276 277#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) /* alternate registers offset */ 278 279#define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */ 280 281/* 282 * Status LED 283 */ 284 285#define CONFIG_SYS_LED_BASE MPC5XXX_GPT7_ENABLE /* Timer 7 GPIO */ 286#ifndef __ASSEMBLY__ 287typedef unsigned int led_id_t; 288 289#define __led_toggle(_msk) \ 290 do { \ 291 *((volatile long *) (CONFIG_SYS_LED_BASE)) ^= (_msk); \ 292 } while(0) 293 294#define __led_set(_msk, _st) \ 295 do { \ 296 if ((_st)) \ 297 *((volatile long *) (CONFIG_SYS_LED_BASE)) &= ~(_msk); \ 298 else \ 299 *((volatile long *) (CONFIG_SYS_LED_BASE)) |= (_msk); \ 300 } while(0) 301 302#define __led_init(_msk, st) \ 303 do { \ 304 *((volatile long *) (CONFIG_SYS_LED_BASE)) |= 0x34; \ 305 } while(0) 306#endif /* __ASSEMBLY__ */ 307 308#endif /* __CONFIG_H */ 309