1/* 2 * (C) Copyright 2000-2005 3 * Stefan Roese, DENX Software Engineering, sr@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8/* 9 * board/config.h - configuration options, board specific 10 */ 11 12#ifndef __CONFIG_H 13#define __CONFIG_H 14 15/* 16 * High Level Configuration Options 17 * (easy to change) 18 */ 19 20#define CONFIG_405GP 1 /* This is a PPC405 CPU */ 21#define CONFIG_WALNUT 1 /* ...on a WALNUT board */ 22 /* ...or on a SYCAMORE board */ 23 24#define CONFIG_SYS_TEXT_BASE 0xFFFC0000 25 26/* 27 * Include common defines/options for all AMCC eval boards 28 */ 29#define CONFIG_HOSTNAME walnut 30#include "amcc-common.h" 31 32#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ 33 34/* 35 * Default environment variables 36 */ 37#define CONFIG_EXTRA_ENV_SETTINGS \ 38 CONFIG_AMCC_DEF_ENV \ 39 CONFIG_AMCC_DEF_ENV_POWERPC \ 40 CONFIG_AMCC_DEF_ENV_PPC_OLD \ 41 CONFIG_AMCC_DEF_ENV_NOR_UPD \ 42 "kernel_addr=fff80000\0" \ 43 "ramdisk_addr=fff80000\0" \ 44 "" 45 46#define CONFIG_PHY_ADDR 1 /* PHY address */ 47#define CONFIG_HAS_ETH0 1 48 49#define CONFIG_RTC_DS174x 1 /* use DS1743 RTC in Walnut */ 50 51/* 52 * Commands additional to the ones defined in amcc-common.h 53 */ 54#define CONFIG_CMD_PCI 55#define CONFIG_CMD_SDRAM 56 57#define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */ 58 59/* 60 * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1. 61 * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31. 62 * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value. 63 * The Linux BASE_BAUD define should match this configuration. 64 * baseBaud = cpuClock/(uartDivisor*16) 65 * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock, 66 * set Linux BASE_BAUD to 403200. 67 */ 68#define CONFIG_CONS_INDEX 1 /* Use UART0 */ 69#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */ 70#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ 71#define CONFIG_SYS_BASE_BAUD 691200 72 73/*----------------------------------------------------------------------- 74 * I2C stuff 75 *----------------------------------------------------------------------- 76 */ 77#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 78 79#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1) 80#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 81#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 82#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 83 84/*----------------------------------------------------------------------- 85 * PCI stuff 86 *----------------------------------------------------------------------- 87 */ 88#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ 89#define PCI_HOST_FORCE 1 /* configure as pci host */ 90#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ 91 92#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 93#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ 94 /* resource configuration */ 95#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 96 97#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ 98#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ 99#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ 100#define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ 101#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ 102#define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */ 103#define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */ 104#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ 105 106/*----------------------------------------------------------------------- 107 * Start addresses for the final memory configuration 108 * (Set up by the startup code) 109 */ 110#define CONFIG_SYS_FLASH_BASE 0xFFF80000 111 112/* 113 * Define here the location of the environment variables (FLASH or NVRAM). 114 * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only 115 * supported for backward compatibility. 116 */ 117#if 1 118#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ 119#else 120#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ 121#endif 122 123/*----------------------------------------------------------------------- 124 * FLASH organization 125 */ 126#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */ 127#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */ 128 129#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 130#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ 131 132#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ 133#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ 134 135#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ 136 137#define CONFIG_SYS_FLASH_ADDR0 0x5555 138#define CONFIG_SYS_FLASH_ADDR1 0x2aaa 139#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char 140 141#ifdef CONFIG_ENV_IS_IN_FLASH 142#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ 143#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE) 144#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ 145 146/* Address and size of Redundant Environment Sector */ 147#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) 148#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 149#endif /* CONFIG_ENV_IS_IN_FLASH */ 150 151/*----------------------------------------------------------------------- 152 * NVRAM organization 153 */ 154#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */ 155#define CONFIG_SYS_NVRAM_SIZE 0x1ff8 /* NVRAM size */ 156 157#ifdef CONFIG_ENV_IS_IN_NVRAM 158#define CONFIG_ENV_SIZE 0x1000 /* Size of Environment vars */ 159#define CONFIG_ENV_ADDR \ 160 (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) /* Env */ 161#endif 162 163/*----------------------------------------------------------------------- 164 * External Bus Controller (EBC) Setup 165 */ 166 167/* Memory Bank 0 (Flash Bank 0) initialization */ 168#define CONFIG_SYS_EBC_PB0AP 0x9B015480 169#define CONFIG_SYS_EBC_PB0CR 0xFFF18000 /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit */ 170 171#define CONFIG_SYS_EBC_PB1AP 0x02815480 172#define CONFIG_SYS_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ 173 174#define CONFIG_SYS_EBC_PB2AP 0x04815A80 175#define CONFIG_SYS_EBC_PB2CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */ 176 177#define CONFIG_SYS_EBC_PB3AP 0x01815280 178#define CONFIG_SYS_EBC_PB3CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */ 179 180#define CONFIG_SYS_EBC_PB7AP 0x01815280 181#define CONFIG_SYS_EBC_PB7CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */ 182 183/*----------------------------------------------------------------------- 184 * External peripheral base address 185 *----------------------------------------------------------------------- 186 */ 187#define CONFIG_SYS_KEY_REG_BASE_ADDR 0xF0100000 188#define CONFIG_SYS_IR_REG_BASE_ADDR 0xF0200000 189#define CONFIG_SYS_FPGA_REG_BASE_ADDR 0xF0300000 190 191/*----------------------------------------------------------------------- 192 * Definitions for initial stack pointer and data area 193 */ 194#define CONFIG_SYS_INIT_DCACHE_CS 4 /* use cs # 4 for data cache memory */ 195 196#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* inside of SDRAM */ 197#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */ 198#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 199#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 200 201/*----------------------------------------------------------------------- 202 * Definitions for Serial Presence Detect EEPROM address 203 * (to get SDRAM settings) 204 */ 205#define SPD_EEPROM_ADDRESS 0x50 206 207#endif /* __CONFIG_H */ 208