uboot/include/faraday/ftpmu010.h
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   1/*
   2 * (C) Copyright 2009 Faraday Technology
   3 * Po-Yu Chuang <ratbert@faraday-tech.com>
   4 *
   5 * SPDX-License-Identifier:     GPL-2.0+
   6 */
   7
   8/*
   9 * Power Management Unit
  10 */
  11#ifndef __FTPMU010_H
  12#define __FTPMU010_H
  13
  14#ifndef __ASSEMBLY__
  15struct ftpmu010 {
  16        unsigned int    IDNMBR0;        /* 0x00 */
  17        unsigned int    reserved0;      /* 0x04 */
  18        unsigned int    OSCC;           /* 0x08 */
  19        unsigned int    PMODE;          /* 0x0C */
  20        unsigned int    PMCR;           /* 0x10 */
  21        unsigned int    PED;            /* 0x14 */
  22        unsigned int    PEDSR;          /* 0x18 */
  23        unsigned int    reserved1;      /* 0x1C */
  24        unsigned int    PMSR;           /* 0x20 */
  25        unsigned int    PGSR;           /* 0x24 */
  26        unsigned int    MFPSR;          /* 0x28 */
  27        unsigned int    MISC;           /* 0x2C */
  28        unsigned int    PDLLCR0;        /* 0x30 */
  29        unsigned int    PDLLCR1;        /* 0x34 */
  30        unsigned int    AHBMCLKOFF;     /* 0x38 */
  31        unsigned int    APBMCLKOFF;     /* 0x3C */
  32        unsigned int    DCSRCR0;        /* 0x40 */
  33        unsigned int    DCSRCR1;        /* 0x44 */
  34        unsigned int    DCSRCR2;        /* 0x48 */
  35        unsigned int    SDRAMHTC;       /* 0x4C */
  36        unsigned int    PSPR0;          /* 0x50 */
  37        unsigned int    PSPR1;          /* 0x54 */
  38        unsigned int    PSPR2;          /* 0x58 */
  39        unsigned int    PSPR3;          /* 0x5C */
  40        unsigned int    PSPR4;          /* 0x60 */
  41        unsigned int    PSPR5;          /* 0x64 */
  42        unsigned int    PSPR6;          /* 0x68 */
  43        unsigned int    PSPR7;          /* 0x6C */
  44        unsigned int    PSPR8;          /* 0x70 */
  45        unsigned int    PSPR9;          /* 0x74 */
  46        unsigned int    PSPR10;         /* 0x78 */
  47        unsigned int    PSPR11;         /* 0x7C */
  48        unsigned int    PSPR12;         /* 0x80 */
  49        unsigned int    PSPR13;         /* 0x84 */
  50        unsigned int    PSPR14;         /* 0x88 */
  51        unsigned int    PSPR15;         /* 0x8C */
  52        unsigned int    AHBDMA_RACCS;   /* 0x90 */
  53        unsigned int    reserved2;      /* 0x94 */
  54        unsigned int    reserved3;      /* 0x98 */
  55        unsigned int    JSS;            /* 0x9C */
  56        unsigned int    CFC_RACC;       /* 0xA0 */
  57        unsigned int    SSP1_RACC;      /* 0xA4 */
  58        unsigned int    UART1TX_RACC;   /* 0xA8 */
  59        unsigned int    UART1RX_RACC;   /* 0xAC */
  60        unsigned int    UART2TX_RACC;   /* 0xB0 */
  61        unsigned int    UART2RX_RACC;   /* 0xB4 */
  62        unsigned int    SDC_RACC;       /* 0xB8 */
  63        unsigned int    I2SAC97_RACC;   /* 0xBC */
  64        unsigned int    IRDATX_RACC;    /* 0xC0 */
  65        unsigned int    reserved4;      /* 0xC4 */
  66        unsigned int    USBD_RACC;      /* 0xC8 */
  67        unsigned int    IRDARX_RACC;    /* 0xCC */
  68        unsigned int    IRDA_RACC;      /* 0xD0 */
  69        unsigned int    ED0_RACC;       /* 0xD4 */
  70        unsigned int    ED1_RACC;       /* 0xD8 */
  71};
  72#endif /* __ASSEMBLY__ */
  73
  74/*
  75 * ID Number 0 Register
  76 */
  77#define FTPMU010_ID_A320A       0x03200000
  78#define FTPMU010_ID_A320C       0x03200010
  79#define FTPMU010_ID_A320D       0x03200030
  80
  81/*
  82 * OSC Control Register
  83 */
  84#define FTPMU010_OSCC_OSCH_TRI          (1 << 11)
  85#define FTPMU010_OSCC_OSCH_STABLE       (1 << 9)
  86#define FTPMU010_OSCC_OSCH_OFF          (1 << 8)
  87
  88#define FTPMU010_OSCC_OSCL_TRI          (1 << 3)
  89#define FTPMU010_OSCC_OSCL_RTCLSEL      (1 << 2)
  90#define FTPMU010_OSCC_OSCL_STABLE       (1 << 1)
  91#define FTPMU010_OSCC_OSCL_OFF          (1 << 0)
  92
  93/*
  94 * Power Mode Register
  95 */
  96#define FTPMU010_PMODE_DIVAHBCLK_MASK   (0x7 << 4)
  97#define FTPMU010_PMODE_DIVAHBCLK_2      (0x0 << 4)
  98#define FTPMU010_PMODE_DIVAHBCLK_3      (0x1 << 4)
  99#define FTPMU010_PMODE_DIVAHBCLK_4      (0x2 << 4)
 100#define FTPMU010_PMODE_DIVAHBCLK_6      (0x3 << 4)
 101#define FTPMU010_PMODE_DIVAHBCLK_8      (0x4 << 4)
 102#define FTPMU010_PMODE_DIVAHBCLK(pmode) (((pmode) >> 4) & 0x7)
 103#define FTPMU010_PMODE_FCS              (1 << 2)
 104#define FTPMU010_PMODE_TURBO            (1 << 1)
 105#define FTPMU010_PMODE_SLEEP            (1 << 0)
 106
 107/*
 108 * Power Manager Status Register
 109 */
 110#define FTPMU010_PMSR_SMR       (1 << 10)
 111
 112#define FTPMU010_PMSR_RDH       (1 << 2)
 113#define FTPMU010_PMSR_PH        (1 << 1)
 114#define FTPMU010_PMSR_CKEHLOW   (1 << 0)
 115
 116/*
 117 * Multi-Function Port Setting Register
 118 */
 119#define FTPMU010_MFPSR_DEBUGSEL         (1 << 17)
 120#define FTPMU010_MFPSR_DMA0PINSEL       (1 << 16)
 121#define FTPMU010_MFPSR_DMA1PINSEL       (1 << 15)
 122#define FTPMU010_MFPSR_MODEMPINSEL      (1 << 14)
 123#define FTPMU010_MFPSR_AC97CLKOUTSEL    (1 << 13)
 124#define FTPMU010_MFPSR_PWM1PINSEL       (1 << 11)
 125#define FTPMU010_MFPSR_PWM0PINSEL       (1 << 10)
 126#define FTPMU010_MFPSR_IRDACLKSEL       (1 << 9)
 127#define FTPMU010_MFPSR_UARTCLKSEL       (1 << 8)
 128#define FTPMU010_MFPSR_SSPCLKSEL        (1 << 6)
 129#define FTPMU010_MFPSR_I2SCLKSEL        (1 << 5)
 130#define FTPMU010_MFPSR_AC97CLKSEL       (1 << 4)
 131#define FTPMU010_MFPSR_AC97PINSEL       (1 << 3)
 132#define FTPMU010_MFPSR_TRIAHBDIS        (1 << 1)
 133#define FTPMU010_MFPSR_TRIAHBDBG        (1 << 0)
 134
 135/*
 136 * PLL/DLL Control Register 0
 137 * Note:
 138 *  1. FTPMU010_PDLLCR0_HCLKOUTDIS:
 139 *      Datasheet indicated it starts at bit #21 which was wrong.
 140 *  2. FTPMU010_PDLLCR0_DLLFRAG:
 141 *      Datasheet indicated it has 2 bit which was wrong.
 142 */
 143#define FTPMU010_PDLLCR0_HCLKOUTDIS(cr0)        (((cr0) & 0xf) << 20)
 144#define FTPMU010_PDLLCR0_DLLFRAG(cr0)           (1 << 19)
 145#define FTPMU010_PDLLCR0_DLLSTSEL               (1 << 18)
 146#define FTPMU010_PDLLCR0_DLLSTABLE              (1 << 17)
 147#define FTPMU010_PDLLCR0_DLLDIS                 (1 << 16)
 148#define FTPMU010_PDLLCR0_PLL1FRANG(cr0)         (((cr0) & 0x3) << 12)
 149#define FTPMU010_PDLLCR0_PLL1NS(cr0)            (((cr0) & 0x1ff) << 3)
 150#define FTPMU010_PDLLCR0_PLL1STSEL              (1 << 2)
 151#define FTPMU010_PDLLCR0_PLL1STABLE             (1 << 1)
 152#define FTPMU010_PDLLCR0_PLL1DIS                (1 << 0)
 153
 154/*
 155 * SDRAM Signal Hold Time Control Register
 156 */
 157#define FTPMU010_SDRAMHTC_RCLK_DLY(x)           (((x) & 0xf) << 28)
 158#define FTPMU010_SDRAMHTC_CTL_WCLK_DLY(x)       (((x) & 0xf) << 24)
 159#define FTPMU010_SDRAMHTC_DAT_WCLK_DLY(x)       (((x) & 0xf) << 20)
 160#define FTPMU010_SDRAMHTC_EBICTRL_DCSR          (1 << 18)
 161#define FTPMU010_SDRAMHTC_EBIDATA_DCSR          (1 << 17)
 162#define FTPMU010_SDRAMHTC_SDRAMCS_DCSR          (1 << 16)
 163#define FTPMU010_SDRAMHTC_SDRAMCTL_DCSR         (1 << 15)
 164#define FTPMU010_SDRAMHTC_CKE_DCSR              (1 << 14)
 165#define FTPMU010_SDRAMHTC_DQM_DCSR              (1 << 13)
 166#define FTPMU010_SDRAMHTC_SDCLK_DCSR            (1 << 12)
 167
 168#ifndef __ASSEMBLY__
 169void ftpmu010_32768osc_enable(void);
 170void ftpmu010_dlldis_disable(void);
 171void ftpmu010_mfpsr_diselect_dev(unsigned int dev);
 172void ftpmu010_mfpsr_select_dev(unsigned int dev);
 173void ftpmu010_sdram_clk_disable(unsigned int cr0);
 174void ftpmu010_sdramhtc_set(unsigned int val);
 175#endif
 176
 177#ifdef __ASSEMBLY__
 178#define FTPMU010_IDNMBR0        0x00
 179#define FTPMU010_reserved0      0x04
 180#define FTPMU010_OSCC           0x08
 181#define FTPMU010_PMODE          0x0C
 182#define FTPMU010_PMCR           0x10
 183#define FTPMU010_PED            0x14
 184#define FTPMU010_PEDSR          0x18
 185#define FTPMU010_reserved1      0x1C
 186#define FTPMU010_PMSR           0x20
 187#define FTPMU010_PGSR           0x24
 188#define FTPMU010_MFPSR          0x28
 189#define FTPMU010_MISC           0x2C
 190#define FTPMU010_PDLLCR0        0x30
 191#define FTPMU010_PDLLCR1        0x34
 192#define FTPMU010_AHBMCLKOFF     0x38
 193#define FTPMU010_APBMCLKOFF     0x3C
 194#define FTPMU010_DCSRCR0        0x40
 195#define FTPMU010_DCSRCR1        0x44
 196#define FTPMU010_DCSRCR2        0x48
 197#define FTPMU010_SDRAMHTC       0x4C
 198#define FTPMU010_PSPR0          0x50
 199#define FTPMU010_PSPR1          0x54
 200#define FTPMU010_PSPR2          0x58
 201#define FTPMU010_PSPR3          0x5C
 202#define FTPMU010_PSPR4          0x60
 203#define FTPMU010_PSPR5          0x64
 204#define FTPMU010_PSPR6          0x68
 205#define FTPMU010_PSPR7          0x6C
 206#define FTPMU010_PSPR8          0x70
 207#define FTPMU010_PSPR9          0x74
 208#define FTPMU010_PSPR10         0x78
 209#define FTPMU010_PSPR11         0x7C
 210#define FTPMU010_PSPR12         0x80
 211#define FTPMU010_PSPR13         0x84
 212#define FTPMU010_PSPR14         0x88
 213#define FTPMU010_PSPR15         0x8C
 214#define FTPMU010_AHBDMA_RACCS   0x90
 215#define FTPMU010_reserved2      0x94
 216#define FTPMU010_reserved3      0x98
 217#define FTPMU010_JSS            0x9C
 218#define FTPMU010_CFC_RACC       0xA0
 219#define FTPMU010_SSP1_RACC      0xA4
 220#define FTPMU010_UART1TX_RACC   0xA8
 221#define FTPMU010_UART1RX_RACC   0xAC
 222#define FTPMU010_UART2TX_RACC   0xB0
 223#define FTPMU010_UART2RX_RACC   0xB4
 224#define FTPMU010_SDC_RACC       0xB8
 225#define FTPMU010_I2SAC97_RACC   0xBC
 226#define FTPMU010_IRDATX_RACC    0xC0
 227#define FTPMU010_reserved4      0xC4
 228#define FTPMU010_USBD_RACC      0xC8
 229#define FTPMU010_IRDARX_RACC    0xCC
 230#define FTPMU010_IRDA_RACC      0xD0
 231#define FTPMU010_ED0_RACC       0xD4
 232#define FTPMU010_ED1_RACC       0xD8
 233#endif /* __ASSEMBLY__ */
 234
 235#endif  /* __FTPMU010_H */
 236