LXR uboot/include/faraday/ftsdmc021.h

   1/*
   2 * (C) Copyright 2009 Faraday Technology
   3 * Po-Yu Chuang <ratbert@faraday-tech.com>
   4 *
   5 * (C) Copyright 2011 Andes Technology Corp
   6 * Macpaul Lin <macpaul@andestech.com>
   7 *
   8 * SPDX-License-Identifier:     GPL-2.0+
   9 */
  10
  11/*
  12 * FTSDMC021 - SDRAM Controller
  13 */
  14#ifndef __FTSDMC021_H
  15#define __FTSDMC021_H
  16
  17#ifndef __ASSEMBLY__
  18struct ftsdmc021 {
  19        unsigned int    tp1;            /* 0x00 - SDRAM Timing Parameter 1 */
  20        unsigned int    tp2;            /* 0x04 - SDRAM Timing Parameter 2 */
  21        unsigned int    cr1;            /* 0x08 - SDRAM Configuration Reg 1 */
  22        unsigned int    cr2;            /* 0x0c - SDRAM Configuration Reg 2 */
  23        unsigned int    bank0_bsr;      /* 0x10 - Ext. Bank Base/Size Reg 0 */
  24        unsigned int    bank1_bsr;      /* 0x14 - Ext. Bank Base/Size Reg 1 */
  25        unsigned int    bank2_bsr;      /* 0x18 - Ext. Bank Base/Size Reg 2 */
  26        unsigned int    bank3_bsr;      /* 0x1c - Ext. Bank Base/Size Reg 3 */
  27        unsigned int    bank4_bsr;      /* 0x20 - Ext. Bank Base/Size Reg 4 */
  28        unsigned int    bank5_bsr;      /* 0x24 - Ext. Bank Base/Size Reg 5 */
  29        unsigned int    bank6_bsr;      /* 0x28 - Ext. Bank Base/Size Reg 6 */
  30        unsigned int    bank7_bsr;      /* 0x2c - Ext. Bank Base/Size Reg 7 */
  31        unsigned int    ragr;           /* 0x30 - Read Arbitration Group Reg */
  32        unsigned int    frr;            /* 0x34 - Flush Request Register */
  33        unsigned int    ebisr;          /* 0x38 - EBI Support Register  */
  34        unsigned int    rsved[25];      /* 0x3c-0x9c - Reserved         */
  35        unsigned int    crr;            /* 0x100 - Controller Revision Reg */
  36        unsigned int    cfr;            /* 0x104 - Controller Feature Reg */
  37};
  38#endif /* __ASSEMBLY__ */
  39
  40/*
  41 * Timing Parameter 1 Register
  42 */
  43#define FTSDMC021_TP1_TCL(x)    ((x) & 0x3)             /* CAS Latency */
  44#define FTSDMC021_TP1_TWR(x)    (((x) & 0x3) << 4)      /* W-Recovery Time */
  45#define FTSDMC021_TP1_TRF(x)    (((x) & 0xf) << 8)      /* Auto-Refresh Cycle */
  46#define FTSDMC021_TP1_TRCD(x)   (((x) & 0x7) << 12)     /* RAS-to-CAS Delay */
  47#define FTSDMC021_TP1_TRP(x)    (((x) & 0xf) << 16)     /* Precharge Cycle */
  48#define FTSDMC021_TP1_TRAS(x)   (((x) & 0xf) << 20)
  49
  50/*
  51 * Timing Parameter 2 Register
  52 */
  53#define FTSDMC021_TP2_REF_INTV(x)       ((x) & 0xffff)  /* Refresh interval */
  54/* b(16:19) - Initial Refresh Times */
  55#define FTSDMC021_TP2_INI_REFT(x)       (((x) & 0xf) << 16)
  56/* b(20:23) - Initial Pre-Charge Times */
  57#define FTSDMC021_TP2_INI_PREC(x)       (((x) & 0xf) << 20)
  58
  59/*
  60 * SDRAM Configuration Register 1
  61 */
  62#define FTSDMC021_CR1_BNKSIZE(x)        ((x) & 0xf)             /* Bank Size  */
  63#define FTSDMC021_CR1_MBW(x)            (((x) & 0x3) << 4)      /* Bus Width  */
  64#define FTSDMC021_CR1_DSZ(x)            (((x) & 0x7) << 8)      /* SDRAM Size */
  65#define FTSDMC021_CR1_DDW(x)            (((x) & 0x3) << 12)     /* Data Width */
  66/* b(16) MA2T: Double Memory Address Cycle Enable */
  67#define FTSDMC021_CR1_MA2T(x)           (1 << 16)
  68/* The value of b(0:3)CR1: 1M-512M, must be power of 2 */
  69#define FTSDMC021_BANK_SIZE(x)          (ffs(x) - 1)
  70
  71/*
  72 * Configuration Register 2
  73 */
  74#define FTSDMC021_CR2_SREF      (1 << 0)        /* Self-Refresh Mode */
  75#define FTSDMC021_CR2_PWDN      (1 << 1)        /* Power Down Operation Mode */
  76#define FTSDMC021_CR2_ISMR      (1 << 2)        /* Start Set-Mode-Register */
  77#define FTSDMC021_CR2_IREF      (1 << 3)        /* Init Refresh Start Flag */
  78#define FTSDMC021_CR2_IPREC     (1 << 4)        /* Init Pre-Charge Start Flag */
  79#define FTSDMC021_CR2_REFTYPE   (1 << 5)
  80
  81/*
  82 * SDRAM External Bank Base/Size Register
  83 */
  84#define FTSDMC021_BANK_ENABLE           (1 << 12)
  85
  86/* 12-bit base address of external bank.
  87 * Default value is 0x800.
  88 * The 12-bit equals to the haddr[31:20] of AHB address bus. */
  89#define FTSDMC021_BANK_BASE(x)          ((x) & 0xfff)
  90
  91/*
  92 * Read Arbitration Grant Window Register
  93 */
  94#define FTSDMC021_RAGR_CH1GW(x)         (((x) & 0xff) << 0)
  95#define FTSDMC021_RAGR_CH2GW(x)         (((x) & 0xff) << 4)
  96#define FTSDMC021_RAGR_CH3GW(x)         (((x) & 0xff) << 8)
  97#define FTSDMC021_RAGR_CH4GW(x)         (((x) & 0xff) << 12)
  98#define FTSDMC021_RAGR_CH5GW(x)         (((x) & 0xff) << 16)
  99#define FTSDMC021_RAGR_CH6GW(x)         (((x) & 0xff) << 20)
 100#define FTSDMC021_RAGR_CH7GW(x)         (((x) & 0xff) << 24)
 101#define FTSDMC021_RAGR_CH8GW(x)         (((x) & 0xff) << 28)
 102
 103/*
 104 * Flush Request Register
 105 */
 106#define FTSDMC021_FRR_FLUSHCHN(x)       (((x) & 0x7) << 0)
 107#define FTSDMC021_FRR_FLUSHCMPLT        (1 << 3)        /* Flush Req Flag */
 108
 109/*
 110 * External Bus Interface Support Register (EBISR)
 111 */
 112#define FTSDMC021_EBISR_MR(x)           ((x) & 0xfff)   /* Far-end mode */
 113#define FTSDMC021_EBISR_PRSMR           (1 << 12)       /* Pre-SMR      */
 114#define FTSDMC021_EBISR_POPREC          (1 << 13)
 115#define FTSDMC021_EBISR_POSMR           (1 << 14)       /* Post-SMR     */
 116
 117/*
 118 * Controller Revision Register (CRR, Read Only)
 119 */
 120#define FTSDMC021_CRR_REV_VER           (((x) >> 0) & 0xff)
 121#define FTSDMC021_CRR_MINOR_VER         (((x) >> 8) & 0xff)
 122#define FTSDMC021_CRR_MAJOR_VER         (((x) >> 16) & 0xff)
 123
 124/*
 125 * Controller Feature Register (CFR, Read Only)
 126 */
 127#define FTSDMC021_CFR_EBNK              (((x) >> 0) & 0xf)
 128#define FTSDMC021_CFR_CHN               (((x) >> 8) & 0xf)
 129#define FTSDMC021_CFR_EBI               (((x) >> 16) & 0x1)
 130#define FTSDMC021_CFR_CH1_FDEPTH        (((x) >> 24) & 0x1)
 131#define FTSDMC021_CFR_CH2_FDEPTH        (((x) >> 25) & 0x1)
 132#define FTSDMC021_CFR_CH3_FDEPTH        (((x) >> 26) & 0x1)
 133#define FTSDMC021_CFR_CH4_FDEPTH        (((x) >> 27) & 0x1)
 134#define FTSDMC021_CFR_CH5_FDEPTH        (((x) >> 28) & 0x1)
 135#define FTSDMC021_CFR_CH6_FDEPTH        (((x) >> 29) & 0x1)
 136#define FTSDMC021_CFR_CH7_FDEPTH        (((x) >> 30) & 0x1)
 137#define FTSDMC021_CFR_CH8_FDEPTH        (((x) >> 31) & 0x1)
 138
 139#endif  /* __FTSDMC021_H */
 140