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10#include <common.h>
11#include <errno.h>
12#include <dm.h>
13#include <fdtdec.h>
14#include <malloc.h>
15#include <dm/device-internal.h>
16#include <dm/root.h>
17#include <dm/util.h>
18#include <dm/test.h>
19#include <dm/uclass-internal.h>
20#include <power/pmic.h>
21#include <power/regulator.h>
22#include <power/sandbox_pmic.h>
23#include <test/ut.h>
24
25DECLARE_GLOBAL_DATA_PTR;
26
27enum {
28 BUCK1,
29 BUCK2,
30 LDO1,
31 LDO2,
32 OUTPUT_COUNT,
33};
34
35enum {
36 DEVNAME = 0,
37 PLATNAME,
38 OUTPUT_NAME_COUNT,
39};
40
41static const char *regulator_names[OUTPUT_COUNT][OUTPUT_NAME_COUNT] = {
42
43 { SANDBOX_BUCK1_DEVNAME, SANDBOX_BUCK1_PLATNAME },
44 { SANDBOX_BUCK2_DEVNAME, SANDBOX_BUCK2_PLATNAME },
45 { SANDBOX_LDO1_DEVNAME, SANDBOX_LDO1_PLATNAME},
46 { SANDBOX_LDO2_DEVNAME, SANDBOX_LDO2_PLATNAME},
47};
48
49
50static int dm_test_power_regulator_get(struct unit_test_state *uts)
51{
52 struct dm_regulator_uclass_platdata *uc_pdata;
53 struct udevice *dev_by_devname;
54 struct udevice *dev_by_platname;
55 const char *devname;
56 const char *platname;
57 int i;
58
59 for (i = 0; i < OUTPUT_COUNT; i++) {
60
61
62
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64 devname = regulator_names[i][DEVNAME];
65 platname = regulator_names[i][PLATNAME];
66
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71 ut_assertok(regulator_get_by_devname(devname, &dev_by_devname));
72 ut_asserteq_str(devname, dev_by_devname->name);
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78 ut_assertok(regulator_get_by_platname(platname, &dev_by_platname));
79 uc_pdata = dev_get_uclass_platdata(dev_by_platname);
80 ut_assert(uc_pdata);
81 ut_asserteq_str(platname, uc_pdata->name);
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87 ut_asserteq_ptr(dev_by_devname, dev_by_platname);
88 }
89
90 return 0;
91}
92DM_TEST(dm_test_power_regulator_get, DM_TESTF_SCAN_FDT);
93
94
95static int dm_test_power_regulator_set_get_voltage(struct unit_test_state *uts)
96{
97 struct dm_regulator_uclass_platdata *uc_pdata;
98 struct udevice *dev;
99 const char *platname;
100 int val_set, val_get;
101
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103 platname = regulator_names[BUCK1][PLATNAME];
104 ut_assertok(regulator_get_by_platname(platname, &dev));
105
106 uc_pdata = dev_get_uclass_platdata(dev);
107 ut_assert(uc_pdata);
108
109 val_set = uc_pdata->min_uV;
110 ut_assertok(regulator_set_value(dev, val_set));
111
112 val_get = regulator_get_value(dev);
113 ut_assert(val_get >= 0);
114
115 ut_asserteq(val_set, val_get);
116
117 return 0;
118}
119DM_TEST(dm_test_power_regulator_set_get_voltage, DM_TESTF_SCAN_FDT);
120
121
122static int dm_test_power_regulator_set_get_current(struct unit_test_state *uts)
123{
124 struct dm_regulator_uclass_platdata *uc_pdata;
125 struct udevice *dev;
126 const char *platname;
127 int val_set, val_get;
128
129
130 platname = regulator_names[LDO1][PLATNAME];
131 ut_assertok(regulator_get_by_platname(platname, &dev));
132
133 uc_pdata = dev_get_uclass_platdata(dev);
134 ut_assert(uc_pdata);
135
136 val_set = uc_pdata->min_uA;
137 ut_assertok(regulator_set_current(dev, val_set));
138
139 val_get = regulator_get_current(dev);
140 ut_assert(val_get >= 0);
141
142 ut_asserteq(val_set, val_get);
143
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145 platname = regulator_names[LDO2][PLATNAME];
146 ut_assertok(regulator_get_by_platname(platname, &dev));
147
148 uc_pdata = dev_get_uclass_platdata(dev);
149 ut_assert(uc_pdata);
150 ut_asserteq(-ENODATA, uc_pdata->min_uA);
151 ut_asserteq(-ENODATA, uc_pdata->max_uA);
152
153
154 ut_asserteq(-ENOSYS, regulator_set_current(dev, 0));
155
156 return 0;
157}
158DM_TEST(dm_test_power_regulator_set_get_current, DM_TESTF_SCAN_FDT);
159
160
161static int dm_test_power_regulator_set_get_enable(struct unit_test_state *uts)
162{
163 const char *platname;
164 struct udevice *dev;
165 bool val_set = true;
166
167
168 platname = regulator_names[LDO1][PLATNAME];
169 ut_assertok(regulator_get_by_platname(platname, &dev));
170 ut_assertok(regulator_set_enable(dev, val_set));
171
172
173 ut_asserteq(regulator_get_enable(dev), val_set);
174
175 return 0;
176}
177DM_TEST(dm_test_power_regulator_set_get_enable, DM_TESTF_SCAN_FDT);
178
179
180static int dm_test_power_regulator_set_get_mode(struct unit_test_state *uts)
181{
182 const char *platname;
183 struct udevice *dev;
184 int val_set = LDO_OM_SLEEP;
185
186
187 platname = regulator_names[LDO1][PLATNAME];
188 ut_assertok(regulator_get_by_platname(platname, &dev));
189 ut_assertok(regulator_set_mode(dev, val_set));
190
191
192 ut_asserteq(regulator_get_mode(dev), val_set);
193
194 return 0;
195}
196DM_TEST(dm_test_power_regulator_set_get_mode, DM_TESTF_SCAN_FDT);
197
198
199static int dm_test_power_regulator_autoset(struct unit_test_state *uts)
200{
201 const char *platname;
202 struct udevice *dev, *dev_autoset;
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212 platname = regulator_names[BUCK1][PLATNAME];
213 ut_assertok(regulator_autoset_by_name(platname, &dev_autoset));
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216 ut_assertok(regulator_get_by_platname(platname, &dev));
217 ut_asserteq_ptr(dev, dev_autoset);
218
219
220 ut_asserteq(regulator_get_value(dev),
221 SANDBOX_BUCK1_AUTOSET_EXPECTED_UV);
222 ut_asserteq(regulator_get_current(dev),
223 SANDBOX_BUCK1_AUTOSET_EXPECTED_UA);
224 ut_asserteq(regulator_get_enable(dev),
225 SANDBOX_BUCK1_AUTOSET_EXPECTED_ENABLE);
226
227 return 0;
228}
229DM_TEST(dm_test_power_regulator_autoset, DM_TESTF_SCAN_FDT);
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237struct setting {
238 int voltage;
239 int current;
240 bool enable;
241};
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248
249static const char *platname_list[] = {
250 SANDBOX_LDO1_PLATNAME,
251 SANDBOX_LDO2_PLATNAME,
252 NULL,
253};
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263static const struct setting expected_setting_list[] = {
264 [0] = {
265 .voltage = SANDBOX_LDO1_AUTOSET_EXPECTED_UV,
266 .current = SANDBOX_LDO1_AUTOSET_EXPECTED_UA,
267 .enable = SANDBOX_LDO1_AUTOSET_EXPECTED_ENABLE,
268 },
269 [1] = {
270 .voltage = SANDBOX_LDO2_AUTOSET_EXPECTED_UV,
271 .current = SANDBOX_LDO2_AUTOSET_EXPECTED_UA,
272 .enable = SANDBOX_LDO2_AUTOSET_EXPECTED_ENABLE,
273 },
274};
275
276static int list_count = ARRAY_SIZE(expected_setting_list);
277
278
279static int dm_test_power_regulator_autoset_list(struct unit_test_state *uts)
280{
281 struct udevice *dev_list[2], *dev;
282 int i;
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300 ut_assertok(regulator_list_autoset(platname_list, dev_list, false));
301
302 for (i = 0; i < list_count; i++) {
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304 ut_assert(dev_list[i]);
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307 ut_assertok(regulator_get_by_platname(platname_list[i], &dev));
308 ut_asserteq_ptr(dev_list[i], dev);
309
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311 ut_asserteq(regulator_get_value(dev_list[i]),
312 expected_setting_list[i].voltage);
313
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315 ut_asserteq(regulator_get_current(dev_list[i]),
316 expected_setting_list[i].current);
317
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319 ut_asserteq(regulator_get_enable(dev_list[i]),
320 expected_setting_list[i].enable);
321 }
322
323 return 0;
324}
325DM_TEST(dm_test_power_regulator_autoset_list, DM_TESTF_SCAN_FDT);
326