1/* 2 * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de) 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7#ifndef AT91_MATRIX_H 8#define AT91_MATRIX_H 9 10#ifdef __ASSEMBLY__ 11 12#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20) 13#define AT91_ASM_MATRIX_CSA0 (ATMEL_BASE_MATRIX + 0x11C) 14#elif defined(CONFIG_AT91SAM9261) 15#define AT91_ASM_MATRIX_CSA0 (ATMEL_BASE_MATRIX + 0x30) 16#elif defined(CONFIG_AT91SAM9263) 17#define AT91_ASM_MATRIX_CSA0 (ATMEL_BASE_MATRIX + 0x120) 18#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) 19#define AT91_ASM_MATRIX_CSA0 (ATMEL_BASE_MATRIX + 0x128) 20#else 21#error AT91_ASM_MATRIX_CSA0 is not definied for current CPU 22#endif 23 24#define AT91_ASM_MATRIX_MCFG ATMEL_BASE_MATRIX 25 26#else 27#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20) 28#define AT91_MATRIX_MASTERS 6 29#define AT91_MATRIX_SLAVES 5 30#elif defined(CONFIG_AT91SAM9261) 31#define AT91_MATRIX_MASTERS 1 32#define AT91_MATRIX_SLAVES 5 33#elif defined(CONFIG_AT91SAM9263) 34#define AT91_MATRIX_MASTERS 9 35#define AT91_MATRIX_SLAVES 7 36#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) 37#define AT91_MATRIX_MASTERS 11 38#define AT91_MATRIX_SLAVES 8 39#else 40#error CPU not supported. Please update at91_matrix.h 41#endif 42 43typedef struct at91_priority { 44 u32 a; 45 u32 b; 46} at91_priority_t; 47 48typedef struct at91_matrix { 49 u32 mcfg[AT91_MATRIX_MASTERS]; 50#if defined(CONFIG_AT91SAM9261) 51 u32 scfg[AT91_MATRIX_SLAVES]; 52 u32 res61_1[3]; 53 u32 tcr; 54 u32 res61_2[2]; 55 u32 csa; 56 u32 pucr; 57 u32 res61_3[114]; 58#else 59 u32 reserve1[16 - AT91_MATRIX_MASTERS]; 60 u32 scfg[AT91_MATRIX_SLAVES]; 61 u32 reserve2[16 - AT91_MATRIX_SLAVES]; 62 at91_priority_t pr[AT91_MATRIX_SLAVES]; 63 u32 reserve3[32 - (2 * AT91_MATRIX_SLAVES)]; 64 u32 mrcr; /* 0x100 Master Remap Control */ 65 u32 reserve4[3]; 66#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) 67 u32 ccr[52]; /* 0x110 - 0x1E0 Chip Configuration */ 68 u32 womr; /* 0x1E4 Write Protect Mode */ 69 u32 wpsr; /* 0x1E8 Write Protect Status */ 70 u32 resg45_1[10]; 71#elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20) 72 u32 res60_1[3]; 73 u32 csa; 74 u32 res60_2[56]; 75#elif defined(CONFIG_AT91SAM9263) 76 u32 res63_1; 77 u32 tcmr; 78 u32 res63_2[2]; 79 u32 csa[2]; 80 u32 res63_3[54]; 81#else 82 u32 reserve5[60]; 83#endif 84#endif 85} at91_matrix_t; 86 87#endif /* __ASSEMBLY__ */ 88 89#define AT91_MATRIX_CSA_DBPUC 0x00000100 90#define AT91_MATRIX_CSA_VDDIOMSEL_1_8V 0x00000000 91#define AT91_MATRIX_CSA_VDDIOMSEL_3_3V 0x00010000 92 93#define AT91_MATRIX_CSA_EBI_CS1A 0x00000002 94#define AT91_MATRIX_CSA_EBI_CS3A 0x00000008 95#define AT91_MATRIX_CSA_EBI_CS4A 0x00000010 96#define AT91_MATRIX_CSA_EBI_CS5A 0x00000020 97 98#define AT91_MATRIX_CSA_EBI1_CS2A 0x00000008 99 100#if defined CONFIG_AT91SAM9261 101/* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ 102#define AT91_MATRIX_MCFG_RCB0 (1 << 0) 103/* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ 104#define AT91_MATRIX_MCFG_RCB1 (1 << 1) 105#endif 106 107/* Undefined Length Burst Type */ 108#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9263) || \ 109 defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) 110#define AT91_MATRIX_MCFG_ULBT_INFINITE 0x00000000 111#define AT91_MATRIX_MCFG_ULBT_SINGLE 0x00000001 112#define AT91_MATRIX_MCFG_ULBT_FOUR 0x00000002 113#define AT91_MATRIX_MCFG_ULBT_EIGHT 0x00000003 114#define AT91_MATRIX_MCFG_ULBT_SIXTEEN 0x00000004 115#endif 116#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) 117#define AT91_MATRIX_MCFG_ULBT_THIRTYTWO 0x00000005 118#define AT91_MATRIX_MCFG_ULBT_SIXTYFOUR 0x00000006 119#define AT91_MATRIX_MCFG_ULBT_128 0x00000007 120#endif 121 122/* Default Master Type */ 123#define AT91_MATRIX_SCFG_DEFMSTR_TYPE_NONE 0x00000000 124#define AT91_MATRIX_SCFG_DEFMSTR_TYPE_LAST 0x00010000 125#define AT91_MATRIX_SCFG_DEFMSTR_TYPE_FIXED 0x00020000 126 127/* Fixed Index of Default Master */ 128#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9263) || \ 129 defined(CONFIG_AT91SAM9M10G45) 130#define AT91_MATRIX_SCFG_FIXED_DEFMSTR(x) ((x & 0xf) << 18) 131#elif defined(CONFIG_AT91SAM9261) || defined(CONFIG_AT91SAM9260) 132#define AT91_MATRIX_SCFG_FIXED_DEFMSTR(x) ((x & 7) << 18) 133#endif 134 135/* Maximum Number of Allowed Cycles for a Burst */ 136#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) 137#define AT91_MATRIX_SCFG_SLOT_CYCLE(x) ((x & 0x1ff) << 0) 138#elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) || \ 139 defined(CONFIG_AT91SAM9263) 140#define AT91_MATRIX_SCFG_SLOT_CYCLE(x) ((x & 0xff) << 0) 141#endif 142 143/* Arbitration Type */ 144#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9263) 145#define AT91_MATRIX_SCFG_ARBT_ROUND_ROBIN 0x00000000 146#define AT91_MATRIX_SCFG_ARBT_FIXED_PRIORITY 0x01000000 147#endif 148 149/* Master Remap Control Register */ 150#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9263) || \ 151 defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) 152/* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ 153#define AT91_MATRIX_MRCR_RCB0 (1 << 0) 154/* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ 155#define AT91_MATRIX_MRCR_RCB1 (1 << 1) 156#endif 157#if defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G45) || \ 158 defined(CONFIG_AT91SAM9M10G45) 159#define AT91_MATRIX_MRCR_RCB2 0x00000004 160#define AT91_MATRIX_MRCR_RCB3 0x00000008 161#define AT91_MATRIX_MRCR_RCB4 0x00000010 162#define AT91_MATRIX_MRCR_RCB5 0x00000020 163#define AT91_MATRIX_MRCR_RCB6 0x00000040 164#define AT91_MATRIX_MRCR_RCB7 0x00000080 165#define AT91_MATRIX_MRCR_RCB8 0x00000100 166#endif 167#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) 168#define AT91_MATRIX_MRCR_RCB9 0x00000200 169#define AT91_MATRIX_MRCR_RCB10 0x00000400 170#define AT91_MATRIX_MRCR_RCB11 0x00000800 171#endif 172 173/* TCM Configuration Register */ 174#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) 175/* Size of ITCM enabled memory block */ 176#define AT91_MATRIX_TCMR_ITCM_0 0x00000000 177#define AT91_MATRIX_TCMR_ITCM_32 0x00000040 178/* Size of DTCM enabled memory block */ 179#define AT91_MATRIX_TCMR_DTCM_0 0x00000000 180#define AT91_MATRIX_TCMR_DTCM_32 0x00000060 181#define AT91_MATRIX_TCMR_DTCM_64 0x00000070 182/* Wait state TCM register */ 183#define AT91_MATRIX_TCMR_TCM_NO_WS 0x00000000 184#define AT91_MATRIX_TCMR_TCM_ONE_WS 0x00000800 185#endif 186#if defined(CONFIG_AT91SAM9263) 187/* Size of ITCM enabled memory block */ 188#define AT91_MATRIX_TCMR_ITCM_0 0x00000000 189#define AT91_MATRIX_TCMR_ITCM_16 0x00000005 190#define AT91_MATRIX_TCMR_ITCM_32 0x00000006 191/* Size of DTCM enabled memory block */ 192#define AT91_MATRIX_TCMR_DTCM_0 0x00000000 193#define AT91_MATRIX_TCMR_DTCM_16 0x00000050 194#define AT91_MATRIX_TCMR_DTCM_32 0x00000060 195#endif 196#if defined(CONFIG_AT91SAM9261) 197/* Size of ITCM enabled memory block */ 198#define AT91_MATRIX_TCMR_ITCM_0 0x00000000 199#define AT91_MATRIX_TCMR_ITCM_16 0x00000005 200#define AT91_MATRIX_TCMR_ITCM_32 0x00000006 201#define AT91_MATRIX_TCMR_ITCM_64 0x00000007 202/* Size of DTCM enabled memory block */ 203#define AT91_MATRIX_TCMR_DTCM_0 0x00000000 204#define AT91_MATRIX_TCMR_DTCM_16 0x00000050 205#define AT91_MATRIX_TCMR_DTCM_32 0x00000060 206#define AT91_MATRIX_TCMR_DTCM_64 0x00000070 207#endif 208 209#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) 210/* Video Mode Configuration Register */ 211#define AT91C_MATRIX_VDEC_SEL_OFF 0x00000000 212#define AT91C_MATRIX_VDEC_SEL_ON 0x00000001 213/* Write Protect Mode Register */ 214#define AT91_MATRIX_WPMR_WP_WPDIS 0x00000000 215#define AT91_MATRIX_WPMR_WP_WPEN 0x00000001 216#define AT91_MATRIX_WPMR_WPKEY 0xFFFFFF00 /* Write Protect KEY */ 217/* Write Protect Status Register */ 218#define AT91_MATRIX_WPSR_NO_WPV 0x00000000 219#define AT91_MATRIX_WPSR_WPV 0x00000001 220#define AT91_MATRIX_WPSR_WPVSRC 0x00FFFF00 /* Write Protect Violation Source */ 221#endif 222 223/* USB Pad Pull-Up Control Register */ 224#if defined(CONFIG_AT91SAM9261) 225#define AT91_MATRIX_USBPUCR_PUON 0x40000000 226#endif 227 228#define AT91_MATRIX_PRA_M0(x) ((x & 3) << 0) /* Master 0 Priority Reg. A*/ 229#define AT91_MATRIX_PRA_M1(x) ((x & 3) << 4) /* Master 1 Priority Reg. A*/ 230#define AT91_MATRIX_PRA_M2(x) ((x & 3) << 8) /* Master 2 Priority Reg. A*/ 231#define AT91_MATRIX_PRA_M3(x) ((x & 3) << 12) /* Master 3 Priority Reg. A*/ 232#define AT91_MATRIX_PRA_M4(x) ((x & 3) << 16) /* Master 4 Priority Reg. A*/ 233#define AT91_MATRIX_PRA_M5(x) ((x & 3) << 20) /* Master 5 Priority Reg. A*/ 234#define AT91_MATRIX_PRA_M6(x) ((x & 3) << 24) /* Master 6 Priority Reg. A*/ 235#define AT91_MATRIX_PRA_M7(x) ((x & 3) << 28) /* Master 7 Priority Reg. A*/ 236#define AT91_MATRIX_PRB_M8(x) ((x & 3) << 0) /* Master 8 Priority Reg. B) */ 237#define AT91_MATRIX_PRB_M9(x) ((x & 3) << 4) /* Master 9 Priority Reg. B) */ 238#define AT91_MATRIX_PRB_M10(x) ((x & 3) << 8) /* Master 10 Priority Reg. B) */ 239 240#endif 241