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7#ifndef _SYS_ENV_LIB_H
8#define _SYS_ENV_LIB_H
9
10#include "../../../drivers/ddr/marvell/a38x/ddr3_init.h"
11#include "../../../drivers/ddr/marvell/a38x/ddr3_hws_hw_training.h"
12
13
14#define COMMON_PHY_BASE_ADDR 0x18300
15
16#define DEVICE_CONFIGURATION_REG0 0x18284
17#define DEVICE_CONFIGURATION_REG1 0x18288
18#define COMMON_PHY_CONFIGURATION1_REG 0x18300
19#define COMMON_PHY_CONFIGURATION2_REG 0x18304
20#define COMMON_PHY_CONFIGURATION4_REG 0x1830c
21#define COMMON_PHY_STATUS1_REG 0x18318
22#define COMMON_PHYS_SELECTORS_REG 0x183fc
23#define SOC_CONTROL_REG1 0x18204
24#define GENERAL_PURPOSE_RESERVED0_REG 0x182e0
25#define GBE_CONFIGURATION_REG 0x18460
26#define DEVICE_SAMPLE_AT_RESET1_REG 0x18600
27#define DEVICE_SAMPLE_AT_RESET2_REG 0x18604
28#define DEV_ID_REG 0x18238
29
30#define CORE_PLL_PARAMETERS_REG 0xe42e0
31#define CORE_PLL_CONFIG_REG 0xe42e4
32
33#define QSGMII_CONTROL_REG1 0x18494
34
35#define DEV_ID_REG_DEVICE_ID_OFFS 16
36#define DEV_ID_REG_DEVICE_ID_MASK 0xffff0000
37
38#define SAR_DEV_ID_OFFS 27
39#define SAR_DEV_ID_MASK 0x7
40
41#define POWER_AND_PLL_CTRL_REG 0xa0004
42#define CALIBRATION_CTRL_REG 0xa0008
43#define DFE_REG0 0xa001c
44#define DFE_REG3 0xa0028
45#define RESET_DFE_REG 0xa0148
46#define LOOPBACK_REG 0xa008c
47#define SYNC_PATTERN_REG 0xa0090
48#define INTERFACE_REG 0xa0094
49#define ISOLATE_REG 0xa0098
50#define MISC_REG 0xa013c
51#define GLUE_REG 0xa0140
52#define GENERATION_DIVIDER_FORCE_REG 0xa0144
53#define PCIE_REG0 0xa0120
54#define LANE_ALIGN_REG0 0xa0124
55#define SQUELCH_FFE_SETTING_REG 0xa0018
56#define G1_SETTINGS_0_REG 0xa0034
57#define G1_SETTINGS_1_REG 0xa0038
58#define G1_SETTINGS_3_REG 0xa0440
59#define G1_SETTINGS_4_REG 0xa0444
60#define G2_SETTINGS_0_REG 0xa003c
61#define G2_SETTINGS_1_REG 0xa0040
62#define G2_SETTINGS_2_REG 0xa00f8
63#define G2_SETTINGS_3_REG 0xa0448
64#define G2_SETTINGS_4_REG 0xa044c
65#define G3_SETTINGS_0_REG 0xa0044
66#define G3_SETTINGS_1_REG 0xa0048
67#define G3_SETTINGS_3_REG 0xa0450
68#define G3_SETTINGS_4_REG 0xa0454
69#define VTHIMPCAL_CTRL_REG 0xa0104
70#define REF_REG0 0xa0134
71#define CAL_REG6 0xa0168
72#define RX_REG2 0xa0184
73#define RX_REG3 0xa0188
74#define PCIE_REG1 0xa0288
75#define PCIE_REG3 0xa0290
76#define LANE_CFG1_REG 0xa0604
77#define LANE_CFG4_REG 0xa0620
78#define LANE_CFG5_REG 0xa0624
79#define GLOBAL_CLK_CTRL 0xa0704
80#define GLOBAL_MISC_CTRL 0xa0718
81#define GLOBAL_CLK_SRC_HI 0xa0710
82
83#define GLOBAL_CLK_CTRL 0xa0704
84#define GLOBAL_MISC_CTRL 0xa0718
85#define GLOBAL_PM_CTRL 0xa0740
86
87
88#define SATA_CTRL_REG_IND_ADDR 0xa80a0
89#define SATA_CTRL_REG_IND_DATA 0xa80a4
90
91#define SATA_VENDOR_PORT_0_REG_ADDR 0xa8178
92#define SATA_VENDOR_PORT_1_REG_ADDR 0xa81f8
93#define SATA_VENDOR_PORT_0_REG_DATA 0xa817c
94#define SATA_VENDOR_PORT_1_REG_DATA 0xa81fc
95
96
97#define POWER_AND_PLL_CTRL_REG_100MHZ_VAL 0x0
98#define POWER_AND_PLL_CTRL_REG_25MHZ_VAL_1 0x1
99#define POWER_AND_PLL_CTRL_REG_25MHZ_VAL_2 0x2
100#define POWER_AND_PLL_CTRL_REG_40MHZ_VAL 0x3
101#define GLOBAL_PM_CTRL_REG_25MHZ_VAL 0x7
102#define GLOBAL_PM_CTRL_REG_40MHZ_VAL 0xc
103#define LANE_CFG4_REG_25MHZ_VAL 0x200
104#define LANE_CFG4_REG_40MHZ_VAL 0x300
105
106#define POWER_AND_PLL_CTRL_REG_MASK (~(0x1f))
107#define GLOBAL_PM_CTRL_REG_MASK (~(0xff))
108#define LANE_CFG4_REG_MASK (~(0x1f00))
109
110#define REF_CLK_SELECTOR_VAL_PEX0(reg_val) (reg_val >> 2) & 0x1
111#define REF_CLK_SELECTOR_VAL_PEX1(reg_val) (reg_val >> 3) & 0x1
112#define REF_CLK_SELECTOR_VAL_PEX2(reg_val) (reg_val >> 30) & 0x1
113#define REF_CLK_SELECTOR_VAL_PEX3(reg_val) (reg_val >> 31) & 0x1
114#define REF_CLK_SELECTOR_VAL(reg_val) (reg_val & 0x1)
115
116#define MAX_SELECTOR_VAL 10
117
118
119
120#ifdef CONFIG_ARMADA_39X
121#define EEPROM_I2C_ADDR 0x50
122#else
123#define EEPROM_I2C_ADDR (sys_env_device_rev_get() == \
124 MV_88F68XX_Z1_ID ? 0x50 : 0x57)
125#endif
126#define RD_GET_MODE_ADDR 0x4c
127#define DB_GET_MODE_SLM1363_ADDR 0x25
128#define DB_GET_MODE_SLM1364_ADDR 0x24
129#define DB381_GET_MODE_SLM1426_1427_ADDR 0x56
130
131
132#define SATR_DB_LANE1_MAX_OPTIONS 7
133#define SATR_DB_LANE1_CFG_MASK 0x7
134#define SATR_DB_LANE1_CFG_OFFSET 0
135#define SATR_DB_LANE2_MAX_OPTIONS 4
136#define SATR_DB_LANE2_CFG_MASK 0x38
137#define SATR_DB_LANE2_CFG_OFFSET 3
138
139
140#define SATR_GP_LANE1_CFG_MASK 0x4
141#define SATR_GP_LANE1_CFG_OFFSET 2
142#define SATR_GP_LANE2_CFG_MASK 0x8
143#define SATR_GP_LANE2_CFG_OFFSET 3
144
145
146#define MPP_CTRL_REG 0x18000
147#define MPP_SET_MASK (~(0xffff))
148#define MPP_SET_DATA (0x1111)
149#define MPP_UART1_SET_MASK (~(0xff000))
150#define MPP_UART1_SET_DATA (0x66000)
151
152#define AVS_DEBUG_CNTR_REG 0xe4124
153#define AVS_DEBUG_CNTR_DEFAULT_VALUE 0x08008073
154
155#define AVS_ENABLED_CONTROL 0xe4130
156#define AVS_LOW_VDD_LIMIT_OFFS 4
157#define AVS_LOW_VDD_LIMIT_MASK (0xff << AVS_LOW_VDD_LIMIT_OFFS)
158#define AVS_LOW_VDD_LIMIT_VAL (0x27 << AVS_LOW_VDD_LIMIT_OFFS)
159
160#define AVS_HIGH_VDD_LIMIT_OFFS 12
161#define AVS_HIGH_VDD_LIMIT_MASK (0xff << AVS_HIGH_VDD_LIMIT_OFFS)
162#define AVS_HIGH_VDD_LIMIT_VAL (0x27 << AVS_HIGH_VDD_LIMIT_OFFS)
163
164
165#define MARVELL_BOARD_ID_MASK 0x10
166
167#define A38X_CUSTOMER_BOARD_ID_BASE 0x0
168#define A38X_CUSTOMER_BOARD_ID0 (A38X_CUSTOMER_BOARD_ID_BASE + 0)
169#define A38X_CUSTOMER_BOARD_ID1 (A38X_CUSTOMER_BOARD_ID_BASE + 1)
170#define A38X_MV_MAX_CUSTOMER_BOARD_ID (A38X_CUSTOMER_BOARD_ID_BASE + 2)
171#define A38X_MV_CUSTOMER_BOARD_NUM (A38X_MV_MAX_CUSTOMER_BOARD_ID - \
172 A38X_CUSTOMER_BOARD_ID_BASE)
173
174
175#define A38X_MARVELL_BOARD_ID_BASE 0x10
176#define RD_NAS_68XX_ID (A38X_MARVELL_BOARD_ID_BASE + 0)
177#define DB_68XX_ID (A38X_MARVELL_BOARD_ID_BASE + 1)
178#define RD_AP_68XX_ID (A38X_MARVELL_BOARD_ID_BASE + 2)
179#define DB_AP_68XX_ID (A38X_MARVELL_BOARD_ID_BASE + 3)
180#define DB_GP_68XX_ID (A38X_MARVELL_BOARD_ID_BASE + 4)
181#define DB_BP_6821_ID (A38X_MARVELL_BOARD_ID_BASE + 5)
182#define DB_AMC_6820_ID (A38X_MARVELL_BOARD_ID_BASE + 6)
183#define A38X_MV_MAX_MARVELL_BOARD_ID (A38X_MARVELL_BOARD_ID_BASE + 7)
184#define A38X_MV_MARVELL_BOARD_NUM (A38X_MV_MAX_MARVELL_BOARD_ID - \
185 A38X_MARVELL_BOARD_ID_BASE)
186
187
188#define A39X_CUSTOMER_BOARD_ID_BASE 0x20
189#define A39X_CUSTOMER_BOARD_ID0 (A39X_CUSTOMER_BOARD_ID_BASE + 0)
190#define A39X_CUSTOMER_BOARD_ID1 (A39X_CUSTOMER_BOARD_ID_BASE + 1)
191#define A39X_MV_MAX_CUSTOMER_BOARD_ID (A39X_CUSTOMER_BOARD_ID_BASE + 2)
192#define A39X_MV_CUSTOMER_BOARD_NUM (A39X_MV_MAX_CUSTOMER_BOARD_ID - \
193 A39X_CUSTOMER_BOARD_ID_BASE)
194
195
196#define A39X_MARVELL_BOARD_ID_BASE 0x30
197#define A39X_DB_69XX_ID (A39X_MARVELL_BOARD_ID_BASE + 0)
198#define A39X_RD_69XX_ID (A39X_MARVELL_BOARD_ID_BASE + 1)
199#define A39X_MV_MAX_MARVELL_BOARD_ID (A39X_MARVELL_BOARD_ID_BASE + 2)
200#define A39X_MV_MARVELL_BOARD_NUM (A39X_MV_MAX_MARVELL_BOARD_ID - \
201 A39X_MARVELL_BOARD_ID_BASE)
202
203#ifdef CONFIG_ARMADA_38X
204#define CUTOMER_BOARD_ID_BASE A38X_CUSTOMER_BOARD_ID_BASE
205#define CUSTOMER_BOARD_ID0 A38X_CUSTOMER_BOARD_ID0
206#define CUSTOMER_BOARD_ID1 A38X_CUSTOMER_BOARD_ID1
207#define MV_MAX_CUSTOMER_BOARD_ID A38X_MV_MAX_CUSTOMER_BOARD_ID
208#define MV_CUSTOMER_BOARD_NUM A38X_MV_CUSTOMER_BOARD_NUM
209#define MARVELL_BOARD_ID_BASE A38X_MARVELL_BOARD_ID_BASE
210#define MV_MAX_MARVELL_BOARD_ID A38X_MV_MAX_MARVELL_BOARD_ID
211#define MV_MARVELL_BOARD_NUM A38X_MV_MARVELL_BOARD_NUM
212#define MV_DEFAULT_BOARD_ID DB_68XX_ID
213#define MV_DEFAULT_DEVICE_ID MV_6811
214#elif defined(CONFIG_ARMADA_39X)
215#define CUTOMER_BOARD_ID_BASE A39X_CUSTOMER_BOARD_ID_BASE
216#define CUSTOMER_BOARD_ID0 A39X_CUSTOMER_BOARD_ID0
217#define CUSTOMER_BOARD_ID1 A39X_CUSTOMER_BOARD_ID1
218#define MV_MAX_CUSTOMER_BOARD_ID A39X_MV_MAX_CUSTOMER_BOARD_ID
219#define MV_CUSTOMER_BOARD_NUM A39X_MV_CUSTOMER_BOARD_NUM
220#define MARVELL_BOARD_ID_BASE A39X_MARVELL_BOARD_ID_BASE
221#define MV_MAX_MARVELL_BOARD_ID A39X_MV_MAX_MARVELL_BOARD_ID
222#define MV_MARVELL_BOARD_NUM A39X_MV_MARVELL_BOARD_NUM
223#define MV_DEFAULT_BOARD_ID A39X_DB_69XX_ID
224#define MV_DEFAULT_DEVICE_ID MV_6920
225#endif
226
227#define MV_INVALID_BOARD_ID 0xffffffff
228
229
230#define DEV_VERSION_ID_REG 0x1823c
231#define REVISON_ID_OFFS 8
232#define REVISON_ID_MASK 0xf00
233
234
235#define MV_88F68XX_Z1_ID 0x0
236#define MV_88F68XX_A0_ID 0x4
237
238#define MV_88F69XX_Z1_ID 0x2
239
240#define MPP_CONTROL_REG(id) (0x18000 + (id * 4))
241#define GPP_DATA_OUT_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x00)
242#define GPP_DATA_OUT_EN_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x04)
243#define GPP_DATA_IN_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x10)
244#define MV_GPP_REGS_BASE(unit) (0x18100 + ((unit) * 0x40))
245
246#define MPP_REG_NUM(GPIO_NUM) (GPIO_NUM / 8)
247#define MPP_MASK(GPIO_NUM) (0xf << 4 * (GPIO_NUM - \
248 (MPP_REG_NUM(GPIO_NUM) * 8)));
249#define GPP_REG_NUM(GPIO_NUM) (GPIO_NUM / 32)
250#define GPP_MASK(GPIO_NUM) (1 << GPIO_NUM % 32)
251
252
253
254#define MV_6810_DEV_ID 0x6810
255#define MV_6811_DEV_ID 0x6811
256#define MV_6820_DEV_ID 0x6820
257#define MV_6828_DEV_ID 0x6828
258
259#define MV_6920_DEV_ID 0x6920
260#define MV_6928_DEV_ID 0x6928
261
262enum {
263 MV_6810,
264 MV_6820,
265 MV_6811,
266 MV_6828,
267 MV_NONE,
268 MV_6920,
269 MV_6928,
270 MV_MAX_DEV_ID,
271};
272
273#define MV_6820_INDEX 0
274#define MV_6810_INDEX 1
275#define MV_6811_INDEX 2
276#define MV_6828_INDEX 3
277
278#define MV_6920_INDEX 0
279#define MV_6928_INDEX 1
280
281#ifdef CONFIG_ARMADA_38X
282#define MAX_DEV_ID_NUM 4
283#else
284#define MAX_DEV_ID_NUM 2
285#endif
286
287#define MV_6820_INDEX 0
288#define MV_6810_INDEX 1
289#define MV_6811_INDEX 2
290#define MV_6828_INDEX 3
291#define MV_6920_INDEX 0
292#define MV_6928_INDEX 1
293
294enum unit_id {
295 PEX_UNIT_ID,
296 ETH_GIG_UNIT_ID,
297 USB3H_UNIT_ID,
298 USB3D_UNIT_ID,
299 SATA_UNIT_ID,
300 QSGMII_UNIT_ID,
301 XAUI_UNIT_ID,
302 RXAUI_UNIT_ID,
303 MAX_UNITS_ID
304};
305
306struct board_wakeup_gpio {
307 u32 board_id;
308 int gpio_num;
309};
310
311enum suspend_wakeup_status {
312 SUSPEND_WAKEUP_DISABLED,
313 SUSPEND_WAKEUP_ENABLED,
314 SUSPEND_WAKEUP_ENABLED_GPIO_DETECTED,
315};
316
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323
324
325#ifdef CONFIG_CUSTOMER_BOARD_SUPPORT
326#ifdef CONFIG_ARMADA_38X
327#define MV_BOARD_WAKEUP_GPIO_INFO { \
328 {A38X_CUSTOMER_BOARD_ID0, -1 }, \
329 {A38X_CUSTOMER_BOARD_ID0, -1 }, \
330};
331#else
332#define MV_BOARD_WAKEUP_GPIO_INFO { \
333 {A39X_CUSTOMER_BOARD_ID0, -1 }, \
334 {A39X_CUSTOMER_BOARD_ID0, -1 }, \
335};
336#endif
337
338#else
339
340#ifdef CONFIG_ARMADA_38X
341#define MV_BOARD_WAKEUP_GPIO_INFO { \
342 {RD_NAS_68XX_ID, -2 }, \
343 {DB_68XX_ID, -1 }, \
344 {RD_AP_68XX_ID, -2 }, \
345 {DB_AP_68XX_ID, -2 }, \
346 {DB_GP_68XX_ID, -2 }, \
347 {DB_BP_6821_ID, -2 }, \
348 {DB_AMC_6820_ID, -2 }, \
349};
350#else
351#define MV_BOARD_WAKEUP_GPIO_INFO { \
352 {A39X_RD_69XX_ID, -1 }, \
353 {A39X_DB_69XX_ID, -1 }, \
354};
355#endif
356#endif
357
358u32 mv_board_tclk_get(void);
359u32 mv_board_id_get(void);
360u32 mv_board_id_index_get(u32 board_id);
361u32 sys_env_unit_max_num_get(enum unit_id unit);
362enum suspend_wakeup_status sys_env_suspend_wakeup_check(void);
363u8 sys_env_device_rev_get(void);
364u32 sys_env_device_id_get(void);
365u16 sys_env_model_get(void);
366struct dlb_config *sys_env_dlb_config_ptr_get(void);
367u32 sys_env_get_cs_ena_from_reg(void);
368
369#endif
370
