LXR uboot/arch/m68k/include/asm/coldfire/mdha.h

   1/*
   2 * Message Digest Hardware Accelerator Memory Map
   3 *
   4 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
   5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   6 *
   7 * SPDX-License-Identifier:     GPL-2.0+
   8 */
   9
  10#ifndef __MDHA_H__
  11#define __MDHA_H__
  12
  13/* Message Digest Hardware Accelerator */
  14typedef struct mdha_ctrl {
  15        u32 mr;                 /* 0x00 MDHA Mode */
  16        u32 cr;                 /* 0x04 Control */
  17        u32 cmd;                /* 0x08 Command */
  18        u32 sr;                 /* 0x0C Status */
  19        u32 isr;                /* 0x10 Interrupt Status */
  20        u32 imr;                /* 0x14 Interrupt Mask */
  21        u32 dsz;                /* 0x1C Data Size */
  22        u32 inp;                /* 0x20 Input FIFO */
  23        u32 res1[3];            /* 0x24 - 0x2F */
  24        u32 mda0;               /* 0x30 Message Digest AO */
  25        u32 mdb0;               /* 0x34 Message Digest BO */
  26        u32 mdc0;               /* 0x38 Message Digest CO */
  27        u32 mdd0;               /* 0x3C Message Digest DO */
  28        u32 mde0;               /* 0x40 Message Digest EO */
  29        u32 mdsz;               /* 0x44 Message Data Size */
  30        u32 res[10];            /* 0x48 - 0x6F */
  31        u32 mda1;               /* 0x70 Message Digest A1 */
  32        u32 mdb1;               /* 0x74 Message Digest B1 */
  33        u32 mdc1;               /* 0x78 Message Digest C1 */
  34        u32 mdd1;               /* 0x7C Message Digest D1 */
  35        u32 mde1;               /* 0x80 Message Digest E1 */
  36} mdha_t;
  37
  38#define MDHA_MR_SSL             (0x00000400)
  39#define MDHA_MR_MACFUL          (0x00000200)
  40#define MDHA_MR_SWAP            (0x00000100)
  41#define MDHA_MR_OPAD            (0x00000080)
  42#define MDHA_MR_IPAD            (0x00000040)
  43#define MDHA_MR_INIT            (0x00000020)
  44#define MDHA_MR_MAC(x)          (((x) & 0x03) << 3)
  45#define MDHA_MR_MAC_MASK        (0xFFFFFFE7)
  46#define MDHA_MR_MAC_EHMAC       (0x00000010)
  47#define MDHA_MR_MAC_HMAC        (0x00000008)
  48#define MDHA_MR_MAC_NONE        (0x00000000)
  49#define MDHA_MR_PDATA           (0x00000004)
  50#define MDHA_MR_ALG             (0x00000001)
  51
  52#define MDHA_CR_DMAL(x)         (((x) & 0x1F) << 16)    /* 532x */
  53#define MDHA_CR_DMAL_MASK       (0xFFE0FFFF)            /* 532x */
  54#define MDHA_CR_END             (0x00000004)            /* 532x */
  55#define MDHA_CR_DMA             (0x00000002)            /* 532x */
  56#define MDHA_CR_IE              (0x00000001)
  57
  58#define MDHA_CMD_GO             (0x00000008)
  59#define MDHA_CMD_CI             (0x00000004)
  60#define MDHA_CMD_RI             (0x00000001)
  61#define MDHA_CMD_SWR            (0x00000001)
  62
  63#define MDHA_SR_IFL(x)          (((x) & 0xFF) << 16)
  64#define MDHA_SR_IFL_MASK        (0xFF00FFFF)
  65#define MDHA_SR_APD(x)          (((x) & 0x7) << 13)
  66#define MDHA_SR_APD_MASK        (0xFFFF1FFF)
  67#define MDHA_SR_FS(x)           (((x) & 0x7) << 8)
  68#define MDHA_SR_FS_MASK         (0xFFFFF8FF)
  69#define MDHA_SR_GNW             (0x00000080)
  70#define MDHA_SR_HSH             (0x00000040)
  71#define MDHA_SR_BUSY            (0x00000010)
  72#define MDHA_SR_RD              (0x00000008)
  73#define MDHA_SR_ERR             (0x00000004)
  74#define MDHA_SR_DONE            (0x00000002)
  75#define MDHA_SR_INT             (0x00000001)
  76
  77#define MDHA_ISR_DRL            (0x00000400)            /* 532x */
  78#define MDHA_ISR_GTDS           (0x00000200)
  79#define MDHA_ISR_ERE            (0x00000100)
  80#define MDHA_ISR_RMDP           (0x00000080)
  81#define MDHA_ISR_DSE            (0x00000020)
  82#define MDHA_ISR_IME            (0x00000010)
  83#define MDHA_ISR_NEIF           (0x00000004)
  84#define MDHA_ISR_IFO            (0x00000001)
  85
  86#endif                          /* __MDHA_H__ */
  87