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6
7#include <common.h>
8#include <asm/fsl_serdes.h>
9#include <asm/processor.h>
10#include <asm/io.h>
11#include "fsl_corenet2_serdes.h"
12
13struct serdes_config {
14 u32 protocol;
15 u8 lanes[SRDS_MAX_LANES];
16};
17
18#ifdef CONFIG_ARCH_T4240
19static const struct serdes_config serdes1_cfg_tbl[] = {
20
21 {1, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
22 XAUI_FM1_MAC9, XAUI_FM1_MAC9,
23 XAUI_FM1_MAC10, XAUI_FM1_MAC10,
24 XAUI_FM1_MAC10, XAUI_FM1_MAC10}},
25 {2, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
26 HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
27 HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
28 HIGIG_FM1_MAC10, HIGIG_FM1_MAC10}},
29 {4, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
30 HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
31 HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
32 HIGIG_FM1_MAC10, HIGIG_FM1_MAC10}},
33 {27, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
34 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
35 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
36 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
37 {28, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
38 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
39 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
40 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4}},
41 {35, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
42 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
43 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
44 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
45 {36, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
46 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
47 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
48 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4}},
49 {37, {NONE, NONE, QSGMII_FM1_B, NONE,
50 NONE, NONE, QSGMII_FM1_A, NONE} },
51 {38, {NONE, NONE, QSGMII_FM1_B, NONE,
52 NONE, NONE, QSGMII_FM1_A, NONE}},
53 {39, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
54 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
55 NONE, NONE, QSGMII_FM1_A, NONE} },
56 {40, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
57 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
58 NONE, NONE, QSGMII_FM1_A, NONE}},
59 {45, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
60 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
61 NONE, NONE, QSGMII_FM1_A, NONE} },
62 {46, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
63 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
64 NONE, NONE, QSGMII_FM1_A, NONE}},
65 {47, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
66 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
67 NONE, NONE, QSGMII_FM1_A, NONE} },
68 {48, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
69 SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
70 NONE, NONE, QSGMII_FM1_A, NONE}},
71 {}
72};
73static const struct serdes_config serdes2_cfg_tbl[] = {
74
75 {1, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
76 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
77 XAUI_FM2_MAC10, XAUI_FM2_MAC10,
78 XAUI_FM2_MAC10, XAUI_FM2_MAC10}},
79 {2, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
80 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
81 HIGIG_FM2_MAC10, HIGIG_FM2_MAC10,
82 HIGIG_FM2_MAC10, HIGIG_FM2_MAC10}},
83 {4, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
84 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
85 HIGIG_FM2_MAC10, HIGIG_FM2_MAC10,
86 HIGIG_FM2_MAC10, HIGIG_FM2_MAC10}},
87 {6, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
88 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
89 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
90 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
91 {7, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
92 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
93 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
94 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
95 {12, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
96 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
97 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
98 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
99 {13, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
100 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
101 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
102 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
103 {14, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
104 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
105 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
106 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
107 {15, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
108 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
109 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
110 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
111 {16, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
112 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
113 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
114 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
115 {21, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
116 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
117 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
118 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
119 {22, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
120 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
121 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
122 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
123 {23, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
124 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
125 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
126 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
127 {24, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
128 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
129 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
130 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
131 {25, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
132 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
133 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
134 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
135 {26, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
136 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
137 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
138 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
139 {27, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
140 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
141 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
142 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
143 {28, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
144 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
145 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
146 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
147 {35, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
148 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
149 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
150 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
151 {36, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
152 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
153 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
154 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
155 {37, {NONE, NONE, QSGMII_FM2_B, NONE,
156 NONE, NONE, QSGMII_FM2_A, NONE} },
157 {38, {NONE, NONE, QSGMII_FM2_B, NONE,
158 NONE, NONE, QSGMII_FM2_A, NONE} },
159 {39, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
160 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
161 NONE, NONE, QSGMII_FM2_A, NONE} },
162 {40, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
163 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
164 NONE, NONE, QSGMII_FM2_A, NONE} },
165 {45, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
166 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
167 NONE, NONE, QSGMII_FM2_A, NONE} },
168 {46, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
169 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
170 NONE, NONE, QSGMII_FM2_A, NONE} },
171 {47, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
172 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
173 NONE, NONE, QSGMII_FM2_A, NONE} },
174 {48, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
175 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
176 NONE, NONE, QSGMII_FM2_A, NONE} },
177 {49, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
178 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
179 NONE, NONE, QSGMII_FM2_A, NONE} },
180 {50, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
181 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
182 NONE, NONE, QSGMII_FM2_A, NONE} },
183 {51, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
184 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
185 NONE, NONE, QSGMII_FM2_A, NONE} },
186 {52, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
187 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
188 NONE, NONE, QSGMII_FM2_A, NONE} },
189 {53, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
190 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
191 NONE, NONE, QSGMII_FM2_A, NONE} },
192 {54, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
193 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
194 NONE, NONE, QSGMII_FM2_A, NONE} },
195 {55, {XFI_FM1_MAC9, XFI_FM1_MAC10,
196 XFI_FM2_MAC10, XFI_FM2_MAC9,
197 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
198 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
199 {56, {XFI_FM1_MAC9, XFI_FM1_MAC10,
200 XFI_FM2_MAC10, XFI_FM2_MAC9,
201 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
202 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
203 {57, {XFI_FM1_MAC9, XFI_FM1_MAC10,
204 XFI_FM2_MAC10, XFI_FM2_MAC9,
205 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
206 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
207 {}
208};
209static const struct serdes_config serdes3_cfg_tbl[] = {
210
211 {1, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
212 {2, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1}},
213 {3, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
214 {4, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2}},
215 {5, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
216 {6, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1}},
217 {7, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
218 {8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
219 {9, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
220 INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN}},
221 {10, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
222 INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN}},
223 {11, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
224 PCIE2, PCIE2, PCIE2, PCIE2} },
225 {12, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
226 PCIE2, PCIE2, PCIE2, PCIE2}},
227 {13, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
228 PCIE2, PCIE2, PCIE2, PCIE2} },
229 {14, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
230 PCIE2, PCIE2, PCIE2, PCIE2}},
231 {15, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
232 SRIO1, SRIO1, SRIO1, SRIO1} },
233 {16, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
234 SRIO1, SRIO1, SRIO1, SRIO1}},
235 {17, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
236 SRIO1, SRIO1, SRIO1, SRIO1}},
237 {18, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
238 SRIO1, SRIO1, SRIO1, SRIO1} },
239 {19, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
240 SRIO1, SRIO1, SRIO1, SRIO1}},
241 {20, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
242 SRIO1, SRIO1, SRIO1, SRIO1}},
243 {}
244};
245static const struct serdes_config serdes4_cfg_tbl[] = {
246
247 {1, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3} },
248 {2, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3}},
249 {3, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4} },
250 {4, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4}},
251 {5, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2} },
252 {6, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2}},
253 {7, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2} },
254 {8, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2}},
255 {9, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2} },
256 {10, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2} },
257 {11, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SATA1, SATA2} },
258 {12, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SATA1, SATA2} },
259 {13, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2} },
260 {14, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2}},
261 {15, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2} },
262 {16, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2}},
263 {18, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, AURORA, AURORA}},
264 {}
265};
266#elif defined(CONFIG_ARCH_T4160)
267static const struct serdes_config serdes1_cfg_tbl[] = {
268
269 {1, {NONE, NONE, NONE, NONE,
270 XAUI_FM1_MAC10, XAUI_FM1_MAC10,
271 XAUI_FM1_MAC10, XAUI_FM1_MAC10} },
272 {2, {NONE, NONE, NONE, NONE,
273 HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
274 HIGIG_FM1_MAC10, HIGIG_FM1_MAC10} },
275 {4, {NONE, NONE, NONE, NONE,
276 HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
277 HIGIG_FM1_MAC10, HIGIG_FM1_MAC10} },
278 {27, {NONE, NONE, NONE, NONE,
279 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
280 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
281 {28, {NONE, NONE, NONE, NONE,
282 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
283 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
284 {35, {NONE, NONE, NONE, NONE,
285 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
286 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
287 {36, {NONE, NONE, NONE, NONE,
288 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
289 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
290 {37, {NONE, NONE, NONE, NONE,
291 NONE, NONE, QSGMII_FM1_A, NONE} },
292 {38, {NONE, NONE, NONE, NONE,
293 NONE, NONE, QSGMII_FM1_A, NONE} },
294 {}
295};
296static const struct serdes_config serdes2_cfg_tbl[] = {
297
298 {6, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
299 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
300 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
301 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
302 {7, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
303 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
304 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
305 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
306 {12, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
307 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
308 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
309 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
310 {13, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
311 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
312 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
313 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
314 {15, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
315 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
316 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
317 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
318 {16, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
319 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
320 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
321 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
322 {21, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
323 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
324 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
325 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
326 {22, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
327 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
328 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
329 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
330 {24, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
331 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
332 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
333 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
334 {25, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
335 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
336 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
337 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
338 {26, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
339 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
340 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
341 NONE, NONE} },
342 {27, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
343 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
344 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
345 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
346 {28, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
347 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
348 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
349 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
350 {35, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
351 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
352 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
353 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
354 {36, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
355 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
356 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
357 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
358 {37, {NONE, NONE, QSGMII_FM2_B, NONE,
359 NONE, NONE, QSGMII_FM2_A, NONE} },
360 {38, {NONE, NONE, QSGMII_FM2_B, NONE,
361 NONE, NONE, QSGMII_FM2_A, NONE} },
362 {39, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
363 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
364 NONE, NONE, QSGMII_FM2_A, NONE} },
365 {40, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
366 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
367 NONE, NONE, QSGMII_FM2_A, NONE} },
368 {45, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
369 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
370 NONE, NONE, QSGMII_FM2_A, NONE} },
371 {46, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
372 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
373 NONE, NONE, QSGMII_FM2_A, NONE} },
374 {47, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
375 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
376 NONE, NONE, QSGMII_FM2_A, NONE} },
377 {48, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
378 SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
379 NONE, NONE, QSGMII_FM2_A, NONE} },
380 {49, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
381 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
382 NONE, NONE, QSGMII_FM2_A, NONE} },
383 {50, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
384 XAUI_FM2_MAC9, XAUI_FM2_MAC9,
385 NONE, NONE, QSGMII_FM2_A, NONE} },
386 {51, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
387 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
388 NONE, NONE, QSGMII_FM2_A, NONE} },
389 {52, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
390 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
391 NONE, NONE, QSGMII_FM2_A, NONE} },
392 {53, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
393 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
394 NONE, NONE, QSGMII_FM2_A, NONE} },
395 {54, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
396 HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
397 NONE, NONE, QSGMII_FM2_A, NONE} },
398 {55, {NONE, XFI_FM1_MAC10,
399 XFI_FM2_MAC10, NONE,
400 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
401 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
402 {56, {NONE, XFI_FM1_MAC10,
403 XFI_FM2_MAC10, NONE,
404 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
405 SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
406 {57, {NONE, XFI_FM1_MAC10,
407 XFI_FM2_MAC10, NONE,
408 SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
409 NONE, NONE} },
410 {}
411};
412static const struct serdes_config serdes3_cfg_tbl[] = {
413
414 {1, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
415 {2, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
416 {3, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
417 {4, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
418 {5, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
419 {6, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
420 {7, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
421 {8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
422 {9, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
423 INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN} },
424 {10, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
425 INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN} },
426 {11, {NONE, NONE, NONE, NONE,
427 PCIE2, PCIE2, PCIE2, PCIE2} },
428 {12, {NONE, NONE, NONE, NONE,
429 PCIE2, PCIE2, PCIE2, PCIE2} },
430 {13, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
431 PCIE2, PCIE2, PCIE2, PCIE2} },
432 {14, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
433 PCIE2, PCIE2, PCIE2, PCIE2} },
434 {15, {NONE, NONE, NONE, NONE,
435 SRIO1, SRIO1, SRIO1, SRIO1} },
436 {16, {NONE, NONE, NONE, NONE,
437 SRIO1, SRIO1, SRIO1, SRIO1} },
438 {17, {NONE, NONE, NONE, NONE,
439 SRIO1, SRIO1, SRIO1, SRIO1} },
440 {18, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
441 SRIO1, SRIO1, SRIO1, SRIO1} },
442 {19, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
443 SRIO1, SRIO1, SRIO1, SRIO1} },
444 {20, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
445 SRIO1, SRIO1, SRIO1, SRIO1} },
446 {}
447};
448static const struct serdes_config serdes4_cfg_tbl[] = {
449
450 {3, {NONE, NONE, NONE, NONE, PCIE4, PCIE4, PCIE4, PCIE4} },
451 {4, {NONE, NONE, NONE, NONE, PCIE4, PCIE4, PCIE4, PCIE4} },
452 {5, {NONE, NONE, NONE, NONE, SRIO2, SRIO2, SRIO2, SRIO2} },
453 {6, {NONE, NONE, NONE, NONE, SRIO2, SRIO2, SRIO2, SRIO2} },
454 {7, {NONE, NONE, NONE, NONE, SRIO2, SRIO2, SRIO2, SRIO2} },
455 {8, {NONE, NONE, NONE, NONE, SRIO2, SRIO2, SRIO2, SRIO2} },
456 {9, {NONE, NONE, NONE, NONE, PCIE4, PCIE4, SATA1, SATA2} },
457 {10, {NONE, NONE, NONE, NONE, PCIE4, PCIE4, SATA1, SATA2} },
458 {11, {NONE, NONE, NONE, NONE, AURORA, AURORA, SATA1, SATA2} },
459 {12, {NONE, NONE, NONE, NONE, AURORA, AURORA, SATA1, SATA2} },
460 {13, {NONE, NONE, NONE, NONE, AURORA, AURORA, SRIO2, SRIO2} },
461 {14, {NONE, NONE, NONE, NONE, AURORA, AURORA, SRIO2, SRIO2} },
462 {15, {NONE, NONE, NONE, NONE, AURORA, AURORA, SRIO2, SRIO2} },
463 {16, {NONE, NONE, NONE, NONE, AURORA, AURORA, SRIO2, SRIO2} },
464 {18, {NONE, NONE, NONE, NONE, AURORA, AURORA, AURORA, AURORA} },
465 {}
466}
467;
468#else
469#error "Need to define SerDes protocol"
470#endif
471static const struct serdes_config *serdes_cfg_tbl[] = {
472 serdes1_cfg_tbl,
473 serdes2_cfg_tbl,
474 serdes3_cfg_tbl,
475 serdes4_cfg_tbl,
476};
477
478enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
479{
480 const struct serdes_config *ptr;
481
482 if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
483 return 0;
484
485 ptr = serdes_cfg_tbl[serdes];
486 while (ptr->protocol) {
487 if (ptr->protocol == cfg)
488 return ptr->lanes[lane];
489 ptr++;
490 }
491 return 0;
492}
493
494int is_serdes_prtcl_valid(int serdes, u32 prtcl)
495{
496 int i;
497 const struct serdes_config *ptr;
498
499 if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
500 return 0;
501
502 ptr = serdes_cfg_tbl[serdes];
503 while (ptr->protocol) {
504 if (ptr->protocol == prtcl)
505 break;
506 ptr++;
507 }
508
509 if (!ptr->protocol)
510 return 0;
511
512 for (i = 0; i < SRDS_MAX_LANES; i++) {
513 if (ptr->lanes[i] != NONE)
514 return 1;
515 }
516
517 return 0;
518}
519
