LXR uboot/board/atmel/at91sam9260ek/at91sam9260ek.c

   1/*
   2 * (C) Copyright 2007-2008
   3 * Stelian Pop <stelian@popies.net>
   4 * Lead Tech Design <www.leadtechdesign.com>
   5 *
   6 * SPDX-License-Identifier:     GPL-2.0+
   7 */
   8
   9#include <common.h>
  10#include <debug_uart.h>
  11#include <asm/io.h>
  12#include <asm/arch/at91sam9260_matrix.h>
  13#include <asm/arch/at91sam9_smc.h>
  14#include <asm/arch/at91_common.h>
  15#include <asm/arch/clk.h>
  16#include <asm/arch/gpio.h>
  17
  18DECLARE_GLOBAL_DATA_PTR;
  19
  20/* ------------------------------------------------------------------------- */
  21/*
  22 * Miscelaneous platform dependent initialisations
  23 */
  24
  25#ifdef CONFIG_CMD_NAND
  26static void at91sam9260ek_nand_hw_init(void)
  27{
  28        struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  29        struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
  30        unsigned long csa;
  31
  32        /* Assign CS3 to NAND/SmartMedia Interface */
  33        csa = readl(&matrix->ebicsa);
  34        csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
  35        writel(csa, &matrix->ebicsa);
  36
  37        /* Configure SMC CS3 for NAND/SmartMedia */
  38        writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
  39                AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
  40                &smc->cs[3].setup);
  41        writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
  42                AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
  43                &smc->cs[3].pulse);
  44        writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
  45                &smc->cs[3].cycle);
  46        writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  47                AT91_SMC_MODE_EXNW_DISABLE |
  48#ifdef CONFIG_SYS_NAND_DBW_16
  49                AT91_SMC_MODE_DBW_16 |
  50#else /* CONFIG_SYS_NAND_DBW_8 */
  51                AT91_SMC_MODE_DBW_8 |
  52#endif
  53                AT91_SMC_MODE_TDF_CYCLE(2),
  54                &smc->cs[3].mode);
  55
  56        /* Configure RDY/BSY */
  57        at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
  58
  59        /* Enable NandFlash */
  60        at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
  61
  62}
  63#endif
  64
  65#ifdef CONFIG_DEBUG_UART_BOARD_INIT
  66void board_debug_uart_init(void)
  67{
  68        at91_seriald_hw_init();
  69}
  70#endif
  71
  72#ifdef CONFIG_BOARD_EARLY_INIT_F
  73int board_early_init_f(void)
  74{
  75#ifdef CONFIG_DEBUG_UART
  76        debug_uart_init();
  77#endif
  78        return 0;
  79}
  80#endif
  81
  82int board_init(void)
  83{
  84        /* adress of boot parameters */
  85        gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  86
  87#ifdef CONFIG_CMD_NAND
  88        at91sam9260ek_nand_hw_init();
  89#endif
  90#ifdef CONFIG_HAS_DATAFLASH
  91        at91_spi0_hw_init((1 << 0) | (1 << 1));
  92#endif
  93
  94        return 0;
  95}
  96
  97int dram_init(void)
  98{
  99        gd->ram_size = get_ram_size(
 100                (void *)CONFIG_SYS_SDRAM_BASE,
 101                CONFIG_SYS_SDRAM_SIZE);
 102        return 0;
 103}
 104
 105#ifdef CONFIG_RESET_PHY_R
 106void reset_phy(void)
 107{
 108}
 109#endif
 110