LXR uboot/board/freescale/m54418twr/m54418twr.c

   1/*
   2 * Copyright 2010-2012 Freescale Semiconductor, Inc.
   3 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   4 *
   5 * SPDX-License-Identifier:     GPL-2.0+
   6 */
   7
   8#include <common.h>
   9#include <spi.h>
  10#include <asm/io.h>
  11#include <asm/immap.h>
  12#include <mmc.h>
  13#include <fsl_esdhc.h>
  14
  15DECLARE_GLOBAL_DATA_PTR;
  16
  17int checkboard(void)
  18{
  19        /*
  20         * need to to:
  21         * Check serial flash size. if 2mb evb, else 8mb demo
  22         */
  23        puts("Board: ");
  24        puts("Freescale MCF54418 Tower System\n");
  25        return 0;
  26};
  27
  28int dram_init(void)
  29{
  30        u32 dramsize;
  31
  32#if defined(CONFIG_SERIAL_BOOT)
  33        /*
  34         * Serial Boot: The dram is already initialized in start.S
  35         * only require to return DRAM size
  36         */
  37        dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
  38#else
  39        sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM);
  40        ccm_t *ccm = (ccm_t *)MMAP_CCM;
  41        gpio_t *gpio = (gpio_t *) MMAP_GPIO;
  42        pm_t *pm = (pm_t *) MMAP_PM;
  43        u32 i;
  44
  45        dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
  46
  47        for (i = 0x13; i < 0x20; i++) {
  48                if (dramsize == (1 << i))
  49                        break;
  50        }
  51
  52        out_8(&pm->pmcr0, 0x2E);
  53        out_8(&gpio->mscr_sdram, 1);
  54
  55        clrbits_be16(&ccm->misccr2, CCM_MISCCR2_FBHALF);
  56        setbits_be16(&ccm->misccr2, CCM_MISCCR2_DDR2CLK);
  57
  58        out_be32(&sdram->rcrcr, 0x40000000);
  59        out_be32(&sdram->padcr, 0x01030203);
  60
  61        out_be32(&sdram->cr00, 0x01010101);
  62        out_be32(&sdram->cr01, 0x00000101);
  63        out_be32(&sdram->cr02, 0x01010100);
  64        out_be32(&sdram->cr03, 0x01010000);
  65        out_be32(&sdram->cr04, 0x00010101);
  66        out_be32(&sdram->cr06, 0x00010100);
  67        out_be32(&sdram->cr07, 0x00000001);
  68        out_be32(&sdram->cr08, 0x01000001);
  69        out_be32(&sdram->cr09, 0x00000100);
  70        out_be32(&sdram->cr10, 0x00010001);
  71        out_be32(&sdram->cr11, 0x00000200);
  72        out_be32(&sdram->cr12, 0x01000002);
  73        out_be32(&sdram->cr13, 0x00000000);
  74        out_be32(&sdram->cr14, 0x00000100);
  75        out_be32(&sdram->cr15, 0x02000100);
  76        out_be32(&sdram->cr16, 0x02000407);
  77        out_be32(&sdram->cr17, 0x02030007);
  78        out_be32(&sdram->cr18, 0x02000100);
  79        out_be32(&sdram->cr19, 0x0A030203);
  80        out_be32(&sdram->cr20, 0x00020708);
  81        out_be32(&sdram->cr21, 0x00050008);
  82        out_be32(&sdram->cr22, 0x04030002);
  83        out_be32(&sdram->cr23, 0x00000004);
  84        out_be32(&sdram->cr24, 0x020A0000);
  85        out_be32(&sdram->cr25, 0x0C00000E);
  86        out_be32(&sdram->cr26, 0x00002004);
  87        out_be32(&sdram->cr28, 0x00100010);
  88        out_be32(&sdram->cr29, 0x00100010);
  89        out_be32(&sdram->cr31, 0x07990000);
  90        out_be32(&sdram->cr40, 0x00000000);
  91        out_be32(&sdram->cr41, 0x00C80064);
  92        out_be32(&sdram->cr42, 0x44520002);
  93        out_be32(&sdram->cr43, 0x00C80023);
  94        out_be32(&sdram->cr45, 0x0000C350);
  95        out_be32(&sdram->cr56, 0x04000000);
  96        out_be32(&sdram->cr57, 0x03000304);
  97        out_be32(&sdram->cr58, 0x40040000);
  98        out_be32(&sdram->cr59, 0xC0004004);
  99        out_be32(&sdram->cr60, 0x0642C000);
 100        out_be32(&sdram->cr61, 0x00000642);
 101        asm("tpf");
 102
 103        out_be32(&sdram->cr09, 0x01000100);
 104
 105        udelay(100);
 106#endif
 107        gd->ram_size = dramsize;
 108
 109        return 0;
 110};
 111
 112int testdram(void)
 113{
 114        return 0;
 115}
 116