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8#include <common.h>
9#include <hwconfig.h>
10#include <i2c.h>
11#include <spi.h>
12#include <libfdt.h>
13#include <fdt_support.h>
14#include <pci.h>
15#include <mpc83xx.h>
16#include <fsl_esdhc.h>
17#include <asm/io.h>
18#include <asm/fsl_serdes.h>
19#include <asm/fsl_mpc83xx_serdes.h>
20
21#include "mpc8308.h"
22
23#include <gdsys_fpga.h>
24
25#include "../common/adv7611.h"
26#include "../common/ch7301.h"
27#include "../common/dp501.h"
28#include "../common/ioep-fpga.h"
29#include "../common/mclink.h"
30#include "../common/osd.h"
31#include "../common/phy.h"
32#include "../common/fanctrl.h"
33
34#include <pca953x.h>
35#include <pca9698.h>
36
37#include <miiphy.h>
38
39DECLARE_GLOBAL_DATA_PTR;
40
41#define MAX_MUX_CHANNELS 2
42
43enum {
44 MCFPGA_DONE = 1 << 0,
45 MCFPGA_INIT_N = 1 << 1,
46 MCFPGA_PROGRAM_N = 1 << 2,
47 MCFPGA_UPDATE_ENABLE_N = 1 << 3,
48 MCFPGA_RESET_N = 1 << 4,
49};
50
51enum {
52 GPIO_MDC = 1 << 14,
53 GPIO_MDIO = 1 << 15,
54};
55
56unsigned int mclink_fpgacount;
57struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
58
59struct {
60 u8 bus;
61 u8 addr;
62} strider_fans[] = CONFIG_STRIDER_FANS;
63
64int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data)
65{
66 int res;
67
68 switch (fpga) {
69 case 0:
70 out_le16(reg, data);
71 break;
72 default:
73 res = mclink_send(fpga - 1, regoff, data);
74 if (res < 0) {
75 printf("mclink_send reg %02lx data %04x returned %d\n",
76 regoff, data, res);
77 return res;
78 }
79 break;
80 }
81
82 return 0;
83}
84
85int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data)
86{
87 int res;
88
89 switch (fpga) {
90 case 0:
91 *data = in_le16(reg);
92 break;
93 default:
94 if (fpga > mclink_fpgacount)
95 return -EINVAL;
96 res = mclink_receive(fpga - 1, regoff, data);
97 if (res < 0) {
98 printf("mclink_receive reg %02lx returned %d\n",
99 regoff, res);
100 return res;
101 }
102 }
103
104 return 0;
105}
106
107int checkboard(void)
108{
109 char *s = getenv("serial#");
110 bool hw_type_cat = pca9698_get_value(0x20, 18);
111
112 puts("Board: ");
113
114 printf("Strider %s", hw_type_cat ? "CAT" : "Fiber");
115
116 if (s != NULL) {
117 puts(", serial# ");
118 puts(s);
119 }
120
121 puts("\n");
122
123 return 0;
124}
125
126int last_stage_init(void)
127{
128 int slaves;
129 unsigned int k;
130 unsigned int mux_ch;
131 unsigned char mclink_controllers_dvi[] = { 0x3c, 0x3d, 0x3e };
132#ifdef CONFIG_STRIDER_CPU
133 unsigned char mclink_controllers_dp[] = { 0x24, 0x25, 0x26 };
134#endif
135 bool hw_type_cat = pca9698_get_value(0x20, 18);
136#ifdef CONFIG_STRIDER_CON_DP
137 bool is_dh = pca9698_get_value(0x20, 25);
138#endif
139 bool ch0_sgmii2_present = false;
140
141
142 pca9698_direction_output(0x20, 8, 0);
143
144
145 pca9698_direction_output(0x20, 10, 1);
146 pca9698_direction_output(0x20, 11, 1);
147
148 ch0_sgmii2_present = !pca9698_get_value(0x20, 37);
149
150
151 for (k = 0; k < ARRAY_SIZE(mclink_controllers_dvi); ++k) {
152 unsigned int ctr = 0;
153 unsigned char *mclink_controllers = mclink_controllers_dvi;
154
155#ifdef CONFIG_STRIDER_CPU
156 if (i2c_probe(mclink_controllers[k])) {
157 mclink_controllers = mclink_controllers_dp;
158 if (i2c_probe(mclink_controllers[k]))
159 continue;
160 }
161#else
162 if (i2c_probe(mclink_controllers[k]))
163 continue;
164#endif
165 while (!(pca953x_get_val(mclink_controllers[k])
166 & MCFPGA_DONE)) {
167 udelay(100000);
168 if (ctr++ > 5) {
169 printf("no done for mclink_controller %d\n", k);
170 break;
171 }
172 }
173
174 pca953x_set_dir(mclink_controllers[k], MCFPGA_RESET_N, 0);
175 pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, 0);
176 udelay(10);
177 pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N,
178 MCFPGA_RESET_N);
179 }
180
181 if (hw_type_cat) {
182 int retval;
183 struct mii_dev *mdiodev = mdio_alloc();
184 if (!mdiodev)
185 return -ENOMEM;
186 strncpy(mdiodev->name, bb_miiphy_buses[0].name, MDIO_NAME_LEN);
187 mdiodev->read = bb_miiphy_read;
188 mdiodev->write = bb_miiphy_write;
189
190 retval = mdio_register(mdiodev);
191 if (retval < 0)
192 return retval;
193 for (mux_ch = 0; mux_ch < MAX_MUX_CHANNELS; ++mux_ch) {
194 if ((mux_ch == 1) && !ch0_sgmii2_present)
195 continue;
196
197 setup_88e1514(bb_miiphy_buses[0].name, mux_ch);
198 }
199 }
200
201
202 udelay(500000);
203
204 mclink_fpgacount = CONFIG_SYS_MCLINK_MAX;
205 slaves = mclink_probe();
206 mclink_fpgacount = 0;
207
208 ioep_fpga_print_info(0);
209
210 if (!adv7611_probe(0))
211 printf(" Advantiv ADV7611 HDMI Receiver\n");
212
213#ifdef CONFIG_STRIDER_CON
214 if (ioep_fpga_has_osd(0))
215 osd_probe(0);
216#endif
217
218#ifdef CONFIG_STRIDER_CON_DP
219 if (ioep_fpga_has_osd(0)) {
220 osd_probe(0);
221 if (is_dh)
222 osd_probe(4);
223 }
224#endif
225
226#ifdef CONFIG_STRIDER_CPU
227 ch7301_probe(0, false);
228 dp501_probe(0, false);
229#endif
230
231 if (slaves <= 0)
232 return 0;
233
234 mclink_fpgacount = slaves;
235
236#ifdef CONFIG_STRIDER_CPU
237
238 for (k = 1; k <= slaves; ++k)
239 FPGA_SET_REG(k, extended_control, 0x10);
240
241 udelay(500000);
242#endif
243
244 for (k = 1; k <= slaves; ++k) {
245 ioep_fpga_print_info(k);
246#ifdef CONFIG_STRIDER_CON
247 if (ioep_fpga_has_osd(k))
248 osd_probe(k);
249#endif
250#ifdef CONFIG_STRIDER_CON_DP
251 if (ioep_fpga_has_osd(k)) {
252 osd_probe(k);
253 if (is_dh)
254 osd_probe(k + 4);
255 }
256#endif
257#ifdef CONFIG_STRIDER_CPU
258 if (!adv7611_probe(k))
259 printf(" Advantiv ADV7611 HDMI Receiver\n");
260 ch7301_probe(k, false);
261 dp501_probe(k, false);
262#endif
263 if (hw_type_cat) {
264 int retval;
265 struct mii_dev *mdiodev = mdio_alloc();
266 if (!mdiodev)
267 return -ENOMEM;
268 strncpy(mdiodev->name, bb_miiphy_buses[k].name,
269 MDIO_NAME_LEN);
270 mdiodev->read = bb_miiphy_read;
271 mdiodev->write = bb_miiphy_write;
272
273 retval = mdio_register(mdiodev);
274 if (retval < 0)
275 return retval;
276 setup_88e1514(bb_miiphy_buses[k].name, 0);
277 }
278 }
279
280 for (k = 0; k < ARRAY_SIZE(strider_fans); ++k) {
281 i2c_set_bus_num(strider_fans[k].bus);
282 init_fan_controller(strider_fans[k].addr);
283 }
284
285 return 0;
286}
287
288
289
290
291
292void fpga_gpio_set(unsigned int bus, int pin)
293{
294 FPGA_SET_REG(bus, gpio.set, pin);
295}
296
297void fpga_gpio_clear(unsigned int bus, int pin)
298{
299 FPGA_SET_REG(bus, gpio.clear, pin);
300}
301
302int fpga_gpio_get(unsigned int bus, int pin)
303{
304 u16 val;
305
306 FPGA_GET_REG(bus, gpio.read, &val);
307
308 return val & pin;
309}
310
311#ifdef CONFIG_STRIDER_CON_DP
312void fpga_control_set(unsigned int bus, int pin)
313{
314 u16 val;
315
316 FPGA_GET_REG(bus, control, &val);
317 FPGA_SET_REG(bus, control, val | pin);
318}
319
320void fpga_control_clear(unsigned int bus, int pin)
321{
322 u16 val;
323
324 FPGA_GET_REG(bus, control, &val);
325 FPGA_SET_REG(bus, control, val & ~pin);
326}
327#endif
328
329void mpc8308_init(void)
330{
331 pca9698_direction_output(0x20, 26, 1);
332}
333
334void mpc8308_set_fpga_reset(unsigned state)
335{
336 pca9698_set_value(0x20, 26, state ? 0 : 1);
337}
338
339void mpc8308_setup_hw(void)
340{
341 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
342
343
344
345
346 setbits_be32(&immr->gpio[0].dir, (1 << (31-11)) | (1 << (31-12)));
347 setbits_be32(&immr->gpio[0].dat, 1 << (31-12));
348}
349
350int mpc8308_get_fpga_done(unsigned fpga)
351{
352 return pca9698_get_value(0x20, 20);
353}
354
355#ifdef CONFIG_FSL_ESDHC
356int board_mmc_init(bd_t *bd)
357{
358 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
359 sysconf83xx_t *sysconf = &immr->sysconf;
360
361
362 out_be32(&sysconf->sdhccr, 0x02000000);
363
364 return fsl_esdhc_mmc_init(bd);
365}
366#endif
367
368static struct pci_region pcie_regions_0[] = {
369 {
370 .bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
371 .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
372 .size = CONFIG_SYS_PCIE1_MEM_SIZE,
373 .flags = PCI_REGION_MEM,
374 },
375 {
376 .bus_start = CONFIG_SYS_PCIE1_IO_BASE,
377 .phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
378 .size = CONFIG_SYS_PCIE1_IO_SIZE,
379 .flags = PCI_REGION_IO,
380 },
381};
382
383void pci_init_board(void)
384{
385 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
386 sysconf83xx_t *sysconf = &immr->sysconf;
387 law83xx_t *pcie_law = sysconf->pcielaw;
388 struct pci_region *pcie_reg[] = { pcie_regions_0 };
389
390 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
391 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
392
393
394 out_be32(&sysconf->pecr1, 0xE0008000);
395 udelay(2000);
396
397
398 out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
399 out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
400
401 mpc83xx_pcie_init(1, pcie_reg);
402}
403
404ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
405{
406 info->portwidth = FLASH_CFI_16BIT;
407 info->chipwidth = FLASH_CFI_BY16;
408 info->interface = FLASH_CFI_X16;
409 return 1;
410}
411
412#if defined(CONFIG_OF_BOARD_SETUP)
413int ft_board_setup(void *blob, bd_t *bd)
414{
415 ft_cpu_setup(blob, bd);
416 fsl_fdt_fixup_dr_usb(blob, bd);
417 fdt_fixup_esdhc(blob, bd);
418
419 return 0;
420}
421#endif
422
423
424
425
426
427struct fpga_mii {
428 unsigned fpga;
429 int mdio;
430} fpga_mii[] = {
431 { 0, 1},
432 { 1, 1},
433 { 2, 1},
434 { 3, 1},
435};
436
437static int mii_dummy_init(struct bb_miiphy_bus *bus)
438{
439 return 0;
440}
441
442static int mii_mdio_active(struct bb_miiphy_bus *bus)
443{
444 struct fpga_mii *fpga_mii = bus->priv;
445
446 if (fpga_mii->mdio)
447 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
448 else
449 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
450
451 return 0;
452}
453
454static int mii_mdio_tristate(struct bb_miiphy_bus *bus)
455{
456 struct fpga_mii *fpga_mii = bus->priv;
457
458 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
459
460 return 0;
461}
462
463static int mii_set_mdio(struct bb_miiphy_bus *bus, int v)
464{
465 struct fpga_mii *fpga_mii = bus->priv;
466
467 if (v)
468 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
469 else
470 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
471
472 fpga_mii->mdio = v;
473
474 return 0;
475}
476
477static int mii_get_mdio(struct bb_miiphy_bus *bus, int *v)
478{
479 u16 gpio;
480 struct fpga_mii *fpga_mii = bus->priv;
481
482 FPGA_GET_REG(fpga_mii->fpga, gpio.read, &gpio);
483
484 *v = ((gpio & GPIO_MDIO) != 0);
485
486 return 0;
487}
488
489static int mii_set_mdc(struct bb_miiphy_bus *bus, int v)
490{
491 struct fpga_mii *fpga_mii = bus->priv;
492
493 if (v)
494 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDC);
495 else
496 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDC);
497
498 return 0;
499}
500
501static int mii_delay(struct bb_miiphy_bus *bus)
502{
503 udelay(1);
504
505 return 0;
506}
507
508struct bb_miiphy_bus bb_miiphy_buses[] = {
509 {
510 .name = "board0",
511 .init = mii_dummy_init,
512 .mdio_active = mii_mdio_active,
513 .mdio_tristate = mii_mdio_tristate,
514 .set_mdio = mii_set_mdio,
515 .get_mdio = mii_get_mdio,
516 .set_mdc = mii_set_mdc,
517 .delay = mii_delay,
518 .priv = &fpga_mii[0],
519 },
520 {
521 .name = "board1",
522 .init = mii_dummy_init,
523 .mdio_active = mii_mdio_active,
524 .mdio_tristate = mii_mdio_tristate,
525 .set_mdio = mii_set_mdio,
526 .get_mdio = mii_get_mdio,
527 .set_mdc = mii_set_mdc,
528 .delay = mii_delay,
529 .priv = &fpga_mii[1],
530 },
531 {
532 .name = "board2",
533 .init = mii_dummy_init,
534 .mdio_active = mii_mdio_active,
535 .mdio_tristate = mii_mdio_tristate,
536 .set_mdio = mii_set_mdio,
537 .get_mdio = mii_get_mdio,
538 .set_mdc = mii_set_mdc,
539 .delay = mii_delay,
540 .priv = &fpga_mii[2],
541 },
542 {
543 .name = "board3",
544 .init = mii_dummy_init,
545 .mdio_active = mii_mdio_active,
546 .mdio_tristate = mii_mdio_tristate,
547 .set_mdio = mii_set_mdio,
548 .get_mdio = mii_get_mdio,
549 .set_mdc = mii_set_mdc,
550 .delay = mii_delay,
551 .priv = &fpga_mii[3],
552 },
553};
554
555int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
556 sizeof(bb_miiphy_buses[0]);
557
