uboot/board/siemens/rut/board.c
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   1/*
   2 * Board functions for TI AM335X based rut board
   3 * (C) Copyright 2013 Siemens Schweiz AG
   4 * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
   5 *
   6 * Based on:
   7 * u-boot:/board/ti/am335x/board.c
   8 *
   9 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
  10 *
  11 * SPDX-License-Identifier:     GPL-2.0+
  12 */
  13
  14#include <common.h>
  15#include <errno.h>
  16#include <spi.h>
  17#include <spl.h>
  18#include <asm/arch/cpu.h>
  19#include <asm/arch/hardware.h>
  20#include <asm/arch/omap.h>
  21#include <asm/arch/ddr_defs.h>
  22#include <asm/arch/clock.h>
  23#include <asm/arch/gpio.h>
  24#include <asm/arch/mmc_host_def.h>
  25#include <asm/arch/sys_proto.h>
  26#include <asm/io.h>
  27#include <asm/emif.h>
  28#include <asm/gpio.h>
  29#include <i2c.h>
  30#include <miiphy.h>
  31#include <cpsw.h>
  32#include <video.h>
  33#include <watchdog.h>
  34#include "board.h"
  35#include "../common/factoryset.h"
  36#include "../../../drivers/video/da8xx-fb.h"
  37
  38DECLARE_GLOBAL_DATA_PTR;
  39
  40/*
  41 * Read header information from EEPROM into global structure.
  42 */
  43static int read_eeprom(void)
  44{
  45        return 0;
  46}
  47
  48#ifdef CONFIG_SPL_BUILD
  49static void board_init_ddr(void)
  50{
  51struct emif_regs rut_ddr3_emif_reg_data = {
  52        .sdram_config = 0x61C04AB2,
  53        .sdram_tim1 = 0x0888A39B,
  54        .sdram_tim2 = 0x26337FDA,
  55        .sdram_tim3 = 0x501F830F,
  56        .emif_ddr_phy_ctlr_1 = 0x6,
  57        .zq_config = 0x50074BE4,
  58        .ref_ctrl = 0x93B,
  59};
  60
  61struct ddr_data rut_ddr3_data = {
  62        .datardsratio0 = 0x3b,
  63        .datawdsratio0 = 0x85,
  64        .datafwsratio0 = 0x100,
  65        .datawrsratio0 = 0xc1,
  66};
  67
  68struct cmd_control rut_ddr3_cmd_ctrl_data = {
  69        .cmd0csratio = 0x40,
  70        .cmd0iclkout = 1,
  71        .cmd1csratio = 0x40,
  72        .cmd1iclkout = 1,
  73        .cmd2csratio = 0x40,
  74        .cmd2iclkout = 1,
  75};
  76
  77const struct ctrl_ioregs ioregs = {
  78        .cm0ioctl               = RUT_IOCTRL_VAL,
  79        .cm1ioctl               = RUT_IOCTRL_VAL,
  80        .cm2ioctl               = RUT_IOCTRL_VAL,
  81        .dt0ioctl               = RUT_IOCTRL_VAL,
  82        .dt1ioctl               = RUT_IOCTRL_VAL,
  83};
  84
  85        config_ddr(DDR_PLL_FREQ, &ioregs, &rut_ddr3_data,
  86                   &rut_ddr3_cmd_ctrl_data, &rut_ddr3_emif_reg_data, 0);
  87}
  88
  89static int request_and_pulse_reset(int gpio, const char *name)
  90{
  91        int ret;
  92        const int delay_us = 2000; /* 2ms */
  93
  94        ret = gpio_request(gpio, name);
  95        if (ret < 0) {
  96                printf("%s: Unable to request %s\n", __func__, name);
  97                goto err;
  98        }
  99
 100        ret = gpio_direction_output(gpio, 0);
 101        if (ret < 0) {
 102                printf("%s: Unable to set %s  as output\n", __func__, name);
 103                goto err_free_gpio;
 104        }
 105
 106        udelay(delay_us);
 107
 108        gpio_set_value(gpio, 1);
 109
 110        return 0;
 111
 112err_free_gpio:
 113        gpio_free(gpio);
 114err:
 115        return ret;
 116}
 117
 118#define GPIO_TO_PIN(bank, gpio)         (32 * (bank) + (gpio))
 119#define ETH_PHY_RESET_GPIO              GPIO_TO_PIN(2, 18)
 120#define MAXTOUCH_RESET_GPIO             GPIO_TO_PIN(3, 18)
 121#define DISPLAY_RESET_GPIO              GPIO_TO_PIN(3, 19)
 122
 123#define REQUEST_AND_PULSE_RESET(N) \
 124                request_and_pulse_reset(N, #N);
 125
 126static void spl_siemens_board_init(void)
 127{
 128        REQUEST_AND_PULSE_RESET(ETH_PHY_RESET_GPIO);
 129        REQUEST_AND_PULSE_RESET(MAXTOUCH_RESET_GPIO);
 130        REQUEST_AND_PULSE_RESET(DISPLAY_RESET_GPIO);
 131}
 132#endif /* if def CONFIG_SPL_BUILD */
 133
 134#if defined(CONFIG_DRIVER_TI_CPSW)
 135static void cpsw_control(int enabled)
 136{
 137        /* VTP can be added here */
 138
 139        return;
 140}
 141
 142static struct cpsw_slave_data cpsw_slaves[] = {
 143        {
 144                .slave_reg_ofs  = 0x208,
 145                .sliver_reg_ofs = 0xd80,
 146                .phy_addr       = 1,
 147                .phy_if         = PHY_INTERFACE_MODE_RMII,
 148        },
 149        {
 150                .slave_reg_ofs  = 0x308,
 151                .sliver_reg_ofs = 0xdc0,
 152                .phy_addr       = 0,
 153                .phy_if         = PHY_INTERFACE_MODE_RMII,
 154        },
 155};
 156
 157static struct cpsw_platform_data cpsw_data = {
 158        .mdio_base              = CPSW_MDIO_BASE,
 159        .cpsw_base              = CPSW_BASE,
 160        .mdio_div               = 0xff,
 161        .channels               = 8,
 162        .cpdma_reg_ofs          = 0x800,
 163        .slaves                 = 1,
 164        .slave_data             = cpsw_slaves,
 165        .ale_reg_ofs            = 0xd00,
 166        .ale_entries            = 1024,
 167        .host_port_reg_ofs      = 0x108,
 168        .hw_stats_reg_ofs       = 0x900,
 169        .bd_ram_ofs             = 0x2000,
 170        .mac_control            = (1 << 5),
 171        .control                = cpsw_control,
 172        .host_port_num          = 0,
 173        .version                = CPSW_CTRL_VERSION_2,
 174};
 175
 176#if defined(CONFIG_DRIVER_TI_CPSW) || \
 177        (defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET))
 178int board_eth_init(bd_t *bis)
 179{
 180        struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
 181        int n = 0;
 182        int rv;
 183
 184#ifndef CONFIG_SPL_BUILD
 185        factoryset_setenv();
 186#endif
 187
 188        /* Set rgmii mode and enable rmii clock to be sourced from chip */
 189        writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel);
 190
 191        rv = cpsw_register(&cpsw_data);
 192        if (rv < 0)
 193                printf("Error %d registering CPSW switch\n", rv);
 194        else
 195                n += rv;
 196        return n;
 197}
 198#endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
 199#endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
 200
 201#if defined(CONFIG_HW_WATCHDOG)
 202static bool hw_watchdog_init_done;
 203static int  hw_watchdog_trigger_level;
 204
 205void hw_watchdog_reset(void)
 206{
 207        if (!hw_watchdog_init_done)
 208                return;
 209
 210        hw_watchdog_trigger_level = hw_watchdog_trigger_level ? 0 : 1;
 211        gpio_set_value(WATCHDOG_TRIGGER_GPIO, hw_watchdog_trigger_level);
 212}
 213
 214void hw_watchdog_init(void)
 215{
 216        gpio_request(WATCHDOG_TRIGGER_GPIO, "watchdog_trigger");
 217        gpio_direction_output(WATCHDOG_TRIGGER_GPIO, hw_watchdog_trigger_level);
 218
 219        hw_watchdog_reset();
 220
 221        hw_watchdog_init_done = 1;
 222}
 223#endif /* defined(CONFIG_HW_WATCHDOG) */
 224
 225#if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
 226static struct da8xx_panel lcd_panels[] = {
 227        /* FORMIKE, 4.3", 480x800, KWH043MC17-F01 */
 228        [0] = {
 229                .name   = "KWH043MC17-F01",
 230                .width  = 480,
 231                .height = 800,
 232                .hfp = 50,              /* no spec, "don't care" values */
 233                .hbp = 50,
 234                .hsw = 50,
 235                .vfp = 50,
 236                .vbp = 50,
 237                .vsw = 50,
 238                .pxl_clk = 35910000,    /* tCYCD=20ns, max 50MHz, 60fps */
 239                .invert_pxl_clk = 1,
 240        },
 241        /* FORMIKE, 4.3", 480x800, KWH043ST20-F01 */
 242        [1] = {
 243                .name   = "KWH043ST20-F01",
 244                .width  = 480,
 245                .height = 800,
 246                .hfp = 50,              /* no spec, "don't care" values */
 247                .hbp = 50,
 248                .hsw = 50,
 249                .vfp = 50,
 250                .vbp = 50,
 251                .vsw = 50,
 252                .pxl_clk = 35910000,    /* tCYCD=20ns, max 50MHz, 60fps */
 253                .invert_pxl_clk = 1,
 254        },
 255        /* Multi-Inno, 4.3", 480x800, MI0430VT-1 */
 256        [2] = {
 257                .name   = "MI0430VT-1",
 258                .width  = 480,
 259                .height = 800,
 260                .hfp = 50,              /* no spec, "don't care" values */
 261                .hbp = 50,
 262                .hsw = 50,
 263                .vfp = 50,
 264                .vbp = 50,
 265                .vsw = 50,
 266                .pxl_clk = 35910000,    /* tCYCD=20ns, max 50MHz, 60fps */
 267                .invert_pxl_clk = 1,
 268        },
 269};
 270
 271static const struct display_panel disp_panels[] = {
 272        [0] = {
 273                WVGA,
 274                16,     /* RGB 888 */
 275                16,
 276                COLOR_ACTIVE,
 277        },
 278        [1] = {
 279                WVGA,
 280                16,     /* RGB 888 */
 281                16,
 282                COLOR_ACTIVE,
 283        },
 284        [2] = {
 285                WVGA,
 286                24,     /* RGB 888 */
 287                16,
 288                COLOR_ACTIVE,
 289        },
 290};
 291
 292static const struct lcd_ctrl_config lcd_cfgs[] = {
 293        [0] = {
 294                &disp_panels[0],
 295                .ac_bias                = 255,
 296                .ac_bias_intrpt         = 0,
 297                .dma_burst_sz           = 16,
 298                .bpp                    = 16,
 299                .fdd                    = 0x80,
 300                .tft_alt_mode           = 0,
 301                .stn_565_mode           = 0,
 302                .mono_8bit_mode         = 0,
 303                .invert_line_clock      = 1,
 304                .invert_frm_clock       = 1,
 305                .sync_edge              = 0,
 306                .sync_ctrl              = 1,
 307                .raster_order           = 0,
 308        },
 309        [1] = {
 310                &disp_panels[1],
 311                .ac_bias                = 255,
 312                .ac_bias_intrpt         = 0,
 313                .dma_burst_sz           = 16,
 314                .bpp                    = 16,
 315                .fdd                    = 0x80,
 316                .tft_alt_mode           = 0,
 317                .stn_565_mode           = 0,
 318                .mono_8bit_mode         = 0,
 319                .invert_line_clock      = 1,
 320                .invert_frm_clock       = 1,
 321                .sync_edge              = 0,
 322                .sync_ctrl              = 1,
 323                .raster_order           = 0,
 324        },
 325        [2] = {
 326                &disp_panels[2],
 327                .ac_bias                = 255,
 328                .ac_bias_intrpt         = 0,
 329                .dma_burst_sz           = 16,
 330                .bpp                    = 24,
 331                .fdd                    = 0x80,
 332                .tft_alt_mode           = 0,
 333                .stn_565_mode           = 0,
 334                .mono_8bit_mode         = 0,
 335                .invert_line_clock      = 1,
 336                .invert_frm_clock       = 1,
 337                .sync_edge              = 0,
 338                .sync_ctrl              = 1,
 339                .raster_order           = 0,
 340        },
 341
 342};
 343
 344/* no console on this board */
 345int board_cfb_skip(void)
 346{
 347        return 1;
 348}
 349
 350#define PLL_GET_M(v) ((v >> 8) & 0x7ff)
 351#define PLL_GET_N(v) (v & 0x7f)
 352
 353static struct dpll_regs dpll_lcd_regs = {
 354        .cm_clkmode_dpll = CM_WKUP + 0x98,
 355        .cm_idlest_dpll = CM_WKUP + 0x48,
 356        .cm_clksel_dpll = CM_WKUP + 0x54,
 357};
 358
 359static int get_clk(struct dpll_regs *dpll_regs)
 360{
 361        unsigned int val;
 362        unsigned int m, n;
 363        int f = 0;
 364
 365        val = readl(dpll_regs->cm_clksel_dpll);
 366        m = PLL_GET_M(val);
 367        n = PLL_GET_N(val);
 368        f = (m * V_OSCK) / n;
 369
 370        return f;
 371};
 372
 373int clk_get(int clk)
 374{
 375        return get_clk(&dpll_lcd_regs);
 376};
 377
 378static int conf_disp_pll(int m, int n)
 379{
 380        struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
 381        struct dpll_params dpll_lcd = {m, n, -1, -1, -1, -1, -1};
 382#if defined(DISPL_PLL_SPREAD_SPECTRUM)
 383        struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP;
 384#endif
 385
 386        u32 *const clk_domains[] = {
 387                &cmper->lcdclkctrl,
 388                0
 389        };
 390        u32 *const clk_modules_explicit_en[] = {
 391                &cmper->lcdclkctrl,
 392                &cmper->lcdcclkstctrl,
 393                &cmper->spi1clkctrl,
 394                0
 395        };
 396        do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
 397
 398        do_setup_dpll(&dpll_lcd_regs, &dpll_lcd);
 399
 400#if defined(DISPL_PLL_SPREAD_SPECTRUM)
 401        writel(0x64, &cmwkup->resv6[3]); /* 0x50 */
 402        writel(0x800, &cmwkup->resv6[2]); /* 0x4c */
 403        writel(readl(&cmwkup->clkmoddplldisp) | CM_CLKMODE_DPLL_SSC_EN_MASK,
 404               &cmwkup->clkmoddplldisp); /* 0x98 */
 405#endif
 406        return 0;
 407}
 408
 409static int set_gpio(int gpio, int state)
 410{
 411        gpio_request(gpio, "temp");
 412        gpio_direction_output(gpio, state);
 413        gpio_set_value(gpio, state);
 414        gpio_free(gpio);
 415        return 0;
 416}
 417
 418static int enable_lcd(void)
 419{
 420        unsigned char buf[1];
 421
 422        set_gpio(BOARD_LCD_RESET, 0);
 423        mdelay(1);
 424        set_gpio(BOARD_LCD_RESET, 1);
 425        mdelay(1);
 426
 427        /* spi lcd init */
 428        kwh043st20_f01_spi_startup(1, 0, 5000000, SPI_MODE_0);
 429
 430        /* backlight on */
 431        buf[0] = 0xf;
 432        i2c_write(0x24, 0x7, 1, buf, 1);
 433        buf[0] = 0x3f;
 434        i2c_write(0x24, 0x8, 1, buf, 1);
 435        return 0;
 436}
 437
 438int arch_early_init_r(void)
 439{
 440        enable_lcd();
 441        return 0;
 442}
 443
 444static int board_video_init(void)
 445{
 446        int i;
 447        int anzdisp = ARRAY_SIZE(lcd_panels);
 448        int display = 1;
 449
 450        for (i = 0; i < anzdisp; i++) {
 451                if (strncmp((const char *)factory_dat.disp_name,
 452                            lcd_panels[i].name,
 453                    strlen((const char *)factory_dat.disp_name)) == 0) {
 454                        printf("DISPLAY: %s\n", factory_dat.disp_name);
 455                        break;
 456                }
 457        }
 458        if (i == anzdisp) {
 459                i = 1;
 460                printf("%s: %s not found, using default %s\n", __func__,
 461                       factory_dat.disp_name, lcd_panels[i].name);
 462        }
 463        conf_disp_pll(24, 1);
 464        da8xx_video_init(&lcd_panels[display], &lcd_cfgs[display],
 465                         lcd_cfgs[display].bpp);
 466
 467        return 0;
 468}
 469#endif /* ifdef CONFIG_VIDEO */
 470
 471#ifdef CONFIG_BOARD_LATE_INIT
 472int board_late_init(void)
 473{
 474        int ret;
 475        char tmp[2 * MAX_STRING_LENGTH + 2];
 476
 477        omap_nand_switch_ecc(1, 8);
 478
 479        if (factory_dat.asn[0] != 0)
 480                sprintf(tmp, "%s_%s", factory_dat.asn,
 481                        factory_dat.comp_version);
 482        else
 483                strcpy(tmp, "QMX7.E38_4.0");
 484
 485        ret = setenv("boardid", tmp);
 486        if (ret)
 487                printf("error setting board id\n");
 488
 489        return 0;
 490}
 491#endif
 492
 493#include "../common/board.c"
 494