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11#include <common.h>
12#include <i2c.h>
13#include <linux/errno.h>
14#include <spl.h>
15#include <usb.h>
16#include <asm/omap_sec_common.h>
17#include <asm/arch/clock.h>
18#include <asm/arch/sys_proto.h>
19#include <asm/arch/mux.h>
20#include <asm/arch/ddr_defs.h>
21#include <asm/arch/gpio.h>
22#include <asm/emif.h>
23#include <asm/omap_common.h>
24#include "../common/board_detect.h"
25#include "board.h"
26#include <power/pmic.h>
27#include <power/tps65218.h>
28#include <power/tps62362.h>
29#include <miiphy.h>
30#include <cpsw.h>
31#include <linux/usb/gadget.h>
32#include <dwc3-uboot.h>
33#include <dwc3-omap-uboot.h>
34#include <ti-usb-phy-uboot.h>
35
36DECLARE_GLOBAL_DATA_PTR;
37
38static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
39
40
41
42
43#ifdef CONFIG_TI_I2C_BOARD_DETECT
44void do_board_detect(void)
45{
46 if (ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
47 CONFIG_EEPROM_CHIP_ADDRESS))
48 printf("ti_i2c_eeprom_init failed\n");
49}
50#endif
51
52#ifndef CONFIG_SKIP_LOWLEVEL_INIT
53
54const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = {
55 {
56 {125, 3, 2, -1, -1, -1, -1},
57 {-1, -1, -1, -1, -1, -1, -1},
58 {125, 3, 1, -1, -1, -1, -1},
59 {150, 3, 1, -1, -1, -1, -1},
60 {125, 2, 1, -1, -1, -1, -1},
61 {625, 11, 1, -1, -1, -1, -1}
62 },
63 {
64 {300, 23, 1, -1, -1, -1, -1},
65 {-1, -1, -1, -1, -1, -1, -1},
66 {600, 23, 1, -1, -1, -1, -1},
67 {720, 23, 1, -1, -1, -1, -1},
68 {800, 23, 1, -1, -1, -1, -1},
69 {1000, 23, 1, -1, -1, -1, -1}
70 },
71 {
72 {300, 24, 1, -1, -1, -1, -1},
73 {-1, -1, -1, -1, -1, -1, -1},
74 {600, 24, 1, -1, -1, -1, -1},
75 {720, 24, 1, -1, -1, -1, -1},
76 {800, 24, 1, -1, -1, -1, -1},
77 {1000, 24, 1, -1, -1, -1, -1}
78 },
79 {
80 {300, 25, 1, -1, -1, -1, -1},
81 {-1, -1, -1, -1, -1, -1, -1},
82 {600, 25, 1, -1, -1, -1, -1},
83 {720, 25, 1, -1, -1, -1, -1},
84 {800, 25, 1, -1, -1, -1, -1},
85 {1000, 25, 1, -1, -1, -1, -1}
86 },
87};
88
89const struct dpll_params dpll_core[NUM_CRYSTAL_FREQ] = {
90 {625, 11, -1, -1, 10, 8, 4},
91 {1000, 23, -1, -1, 10, 8, 4},
92 {1000, 24, -1, -1, 10, 8, 4},
93 {1000, 25, -1, -1, 10, 8, 4}
94};
95
96const struct dpll_params dpll_per[NUM_CRYSTAL_FREQ] = {
97 {400, 7, 5, -1, -1, -1, -1},
98 {400, 9, 5, -1, -1, -1, -1},
99 {384, 9, 5, -1, -1, -1, -1},
100 {480, 12, 5, -1, -1, -1, -1}
101};
102
103const struct dpll_params epos_evm_dpll_ddr[NUM_CRYSTAL_FREQ] = {
104 {665, 47, 1, -1, 4, -1, -1},
105 {133, 11, 1, -1, 4, -1, -1},
106 {266, 24, 1, -1, 4, -1, -1},
107 {133, 12, 1, -1, 4, -1, -1}
108};
109
110const struct dpll_params gp_evm_dpll_ddr = {
111 50, 2, 1, -1, 2, -1, -1};
112
113static const struct dpll_params idk_dpll_ddr = {
114 400, 23, 1, -1, 2, -1, -1
115};
116
117static const u32 ext_phy_ctrl_const_base_lpddr2[] = {
118 0x00500050,
119 0x00350035,
120 0x00350035,
121 0x00350035,
122 0x00350035,
123 0x00350035,
124 0x00000000,
125 0x00000000,
126 0x00000000,
127 0x00000000,
128 0x00000000,
129 0x00000000,
130 0x00000000,
131 0x00000000,
132 0x00000000,
133 0x00000000,
134 0x00000000,
135 0x00000000,
136 0x40001000,
137 0x08102040
138};
139
140const struct ctrl_ioregs ioregs_lpddr2 = {
141 .cm0ioctl = LPDDR2_ADDRCTRL_IOCTRL_VALUE,
142 .cm1ioctl = LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE,
143 .cm2ioctl = LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE,
144 .dt0ioctl = LPDDR2_DATA0_IOCTRL_VALUE,
145 .dt1ioctl = LPDDR2_DATA0_IOCTRL_VALUE,
146 .dt2ioctrl = LPDDR2_DATA0_IOCTRL_VALUE,
147 .dt3ioctrl = LPDDR2_DATA0_IOCTRL_VALUE,
148 .emif_sdram_config_ext = 0x1,
149};
150
151const struct emif_regs emif_regs_lpddr2 = {
152 .sdram_config = 0x808012BA,
153 .ref_ctrl = 0x0000040D,
154 .sdram_tim1 = 0xEA86B411,
155 .sdram_tim2 = 0x103A094A,
156 .sdram_tim3 = 0x0F6BA37F,
157 .read_idle_ctrl = 0x00050000,
158 .zq_config = 0x50074BE4,
159 .temp_alert_config = 0x0,
160 .emif_rd_wr_lvl_rmp_win = 0x0,
161 .emif_rd_wr_lvl_rmp_ctl = 0x0,
162 .emif_rd_wr_lvl_ctl = 0x0,
163 .emif_ddr_phy_ctlr_1 = 0x0E284006,
164 .emif_rd_wr_exec_thresh = 0x80000405,
165 .emif_ddr_ext_phy_ctrl_1 = 0x04010040,
166 .emif_ddr_ext_phy_ctrl_2 = 0x00500050,
167 .emif_ddr_ext_phy_ctrl_3 = 0x00500050,
168 .emif_ddr_ext_phy_ctrl_4 = 0x00500050,
169 .emif_ddr_ext_phy_ctrl_5 = 0x00500050,
170 .emif_prio_class_serv_map = 0x80000001,
171 .emif_connect_id_serv_1_map = 0x80000094,
172 .emif_connect_id_serv_2_map = 0x00000000,
173 .emif_cos_config = 0x000FFFFF
174};
175
176const struct ctrl_ioregs ioregs_ddr3 = {
177 .cm0ioctl = DDR3_ADDRCTRL_IOCTRL_VALUE,
178 .cm1ioctl = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE,
179 .cm2ioctl = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE,
180 .dt0ioctl = DDR3_DATA0_IOCTRL_VALUE,
181 .dt1ioctl = DDR3_DATA0_IOCTRL_VALUE,
182 .dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE,
183 .dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE,
184 .emif_sdram_config_ext = 0xc163,
185};
186
187const struct emif_regs ddr3_emif_regs_400Mhz = {
188 .sdram_config = 0x638413B2,
189 .ref_ctrl = 0x00000C30,
190 .sdram_tim1 = 0xEAAAD4DB,
191 .sdram_tim2 = 0x266B7FDA,
192 .sdram_tim3 = 0x107F8678,
193 .read_idle_ctrl = 0x00050000,
194 .zq_config = 0x50074BE4,
195 .temp_alert_config = 0x0,
196 .emif_ddr_phy_ctlr_1 = 0x0E004008,
197 .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
198 .emif_ddr_ext_phy_ctrl_2 = 0x00400040,
199 .emif_ddr_ext_phy_ctrl_3 = 0x00400040,
200 .emif_ddr_ext_phy_ctrl_4 = 0x00400040,
201 .emif_ddr_ext_phy_ctrl_5 = 0x00400040,
202 .emif_rd_wr_lvl_rmp_win = 0x0,
203 .emif_rd_wr_lvl_rmp_ctl = 0x0,
204 .emif_rd_wr_lvl_ctl = 0x0,
205 .emif_rd_wr_exec_thresh = 0x80000405,
206 .emif_prio_class_serv_map = 0x80000001,
207 .emif_connect_id_serv_1_map = 0x80000094,
208 .emif_connect_id_serv_2_map = 0x00000000,
209 .emif_cos_config = 0x000FFFFF
210};
211
212
213const struct emif_regs ddr3_emif_regs_400Mhz_beta = {
214 .sdram_config = 0x638413B2,
215 .ref_ctrl = 0x00000C30,
216 .sdram_tim1 = 0xEAAAD4DB,
217 .sdram_tim2 = 0x266B7FDA,
218 .sdram_tim3 = 0x107F8678,
219 .read_idle_ctrl = 0x00050000,
220 .zq_config = 0x50074BE4,
221 .temp_alert_config = 0x0,
222 .emif_ddr_phy_ctlr_1 = 0x0E004008,
223 .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
224 .emif_ddr_ext_phy_ctrl_2 = 0x00000065,
225 .emif_ddr_ext_phy_ctrl_3 = 0x00000091,
226 .emif_ddr_ext_phy_ctrl_4 = 0x000000B5,
227 .emif_ddr_ext_phy_ctrl_5 = 0x000000E5,
228 .emif_rd_wr_exec_thresh = 0x80000405,
229 .emif_prio_class_serv_map = 0x80000001,
230 .emif_connect_id_serv_1_map = 0x80000094,
231 .emif_connect_id_serv_2_map = 0x00000000,
232 .emif_cos_config = 0x000FFFFF
233};
234
235
236const struct emif_regs ddr3_emif_regs_400Mhz_production = {
237 .sdram_config = 0x638413B2,
238 .ref_ctrl = 0x00000C30,
239 .sdram_tim1 = 0xEAAAD4DB,
240 .sdram_tim2 = 0x266B7FDA,
241 .sdram_tim3 = 0x107F8678,
242 .read_idle_ctrl = 0x00050000,
243 .zq_config = 0x50074BE4,
244 .temp_alert_config = 0x0,
245 .emif_ddr_phy_ctlr_1 = 0x0E004008,
246 .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
247 .emif_ddr_ext_phy_ctrl_2 = 0x00000066,
248 .emif_ddr_ext_phy_ctrl_3 = 0x00000091,
249 .emif_ddr_ext_phy_ctrl_4 = 0x000000B9,
250 .emif_ddr_ext_phy_ctrl_5 = 0x000000E6,
251 .emif_rd_wr_exec_thresh = 0x80000405,
252 .emif_prio_class_serv_map = 0x80000001,
253 .emif_connect_id_serv_1_map = 0x80000094,
254 .emif_connect_id_serv_2_map = 0x00000000,
255 .emif_cos_config = 0x000FFFFF
256};
257
258static const struct emif_regs ddr3_sk_emif_regs_400Mhz = {
259 .sdram_config = 0x638413b2,
260 .sdram_config2 = 0x00000000,
261 .ref_ctrl = 0x00000c30,
262 .sdram_tim1 = 0xeaaad4db,
263 .sdram_tim2 = 0x266b7fda,
264 .sdram_tim3 = 0x107f8678,
265 .read_idle_ctrl = 0x00050000,
266 .zq_config = 0x50074be4,
267 .temp_alert_config = 0x0,
268 .emif_ddr_phy_ctlr_1 = 0x0e084008,
269 .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
270 .emif_ddr_ext_phy_ctrl_2 = 0x89,
271 .emif_ddr_ext_phy_ctrl_3 = 0x90,
272 .emif_ddr_ext_phy_ctrl_4 = 0x8e,
273 .emif_ddr_ext_phy_ctrl_5 = 0x8d,
274 .emif_rd_wr_lvl_rmp_win = 0x0,
275 .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
276 .emif_rd_wr_lvl_ctl = 0x00000000,
277 .emif_rd_wr_exec_thresh = 0x80000000,
278 .emif_prio_class_serv_map = 0x80000001,
279 .emif_connect_id_serv_1_map = 0x80000094,
280 .emif_connect_id_serv_2_map = 0x00000000,
281 .emif_cos_config = 0x000FFFFF
282};
283
284static const struct emif_regs ddr3_idk_emif_regs_400Mhz = {
285 .sdram_config = 0x61a11b32,
286 .sdram_config2 = 0x00000000,
287 .ref_ctrl = 0x00000c30,
288 .sdram_tim1 = 0xeaaad4db,
289 .sdram_tim2 = 0x266b7fda,
290 .sdram_tim3 = 0x107f8678,
291 .read_idle_ctrl = 0x00050000,
292 .zq_config = 0x50074be4,
293 .temp_alert_config = 0x00000000,
294 .emif_ddr_phy_ctlr_1 = 0x00008009,
295 .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
296 .emif_ddr_ext_phy_ctrl_2 = 0x00000040,
297 .emif_ddr_ext_phy_ctrl_3 = 0x0000003e,
298 .emif_ddr_ext_phy_ctrl_4 = 0x00000051,
299 .emif_ddr_ext_phy_ctrl_5 = 0x00000051,
300 .emif_rd_wr_lvl_rmp_win = 0x00000000,
301 .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
302 .emif_rd_wr_lvl_ctl = 0x00000000,
303 .emif_rd_wr_exec_thresh = 0x00000405,
304 .emif_prio_class_serv_map = 0x00000000,
305 .emif_connect_id_serv_1_map = 0x00000000,
306 .emif_connect_id_serv_2_map = 0x00000000,
307 .emif_cos_config = 0x00ffffff
308};
309
310void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
311{
312 if (board_is_eposevm()) {
313 *regs = ext_phy_ctrl_const_base_lpddr2;
314 *size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2);
315 }
316
317 return;
318}
319
320const struct dpll_params *get_dpll_ddr_params(void)
321{
322 int ind = get_sys_clk_index();
323
324 if (board_is_eposevm())
325 return &epos_evm_dpll_ddr[ind];
326 else if (board_is_evm() || board_is_sk())
327 return &gp_evm_dpll_ddr;
328 else if (board_is_idk())
329 return &idk_dpll_ddr;
330
331 printf(" Board '%s' not supported\n", board_ti_get_name());
332 return NULL;
333}
334
335
336
337
338
339
340
341
342
343
344
345
346static int get_opp_offset(int max_off, int min_off)
347{
348 struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
349 int opp, offset, i;
350
351
352 opp = readl(&ctrl->dev_attr) & ~0xFFFFF000;
353
354 for (i = max_off; i >= min_off; i--) {
355 offset = opp & (1 << i);
356 if (!offset)
357 return i;
358 }
359
360 return min_off;
361}
362
363const struct dpll_params *get_dpll_mpu_params(void)
364{
365 int opp = get_opp_offset(DEV_ATTR_MAX_OFFSET, DEV_ATTR_MIN_OFFSET);
366 u32 ind = get_sys_clk_index();
367
368 return &dpll_mpu[ind][opp];
369}
370
371const struct dpll_params *get_dpll_core_params(void)
372{
373 int ind = get_sys_clk_index();
374
375 return &dpll_core[ind];
376}
377
378const struct dpll_params *get_dpll_per_params(void)
379{
380 int ind = get_sys_clk_index();
381
382 return &dpll_per[ind];
383}
384
385void scale_vcores_generic(u32 m)
386{
387 int mpu_vdd;
388
389 if (i2c_probe(TPS65218_CHIP_PM))
390 return;
391
392 switch (m) {
393 case 1000:
394 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1330MV;
395 break;
396 case 800:
397 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1260MV;
398 break;
399 case 720:
400 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1200MV;
401 break;
402 case 600:
403 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1100MV;
404 break;
405 case 300:
406 mpu_vdd = TPS65218_DCDC_VOLT_SEL_0950MV;
407 break;
408 default:
409 puts("Unknown MPU clock, not scaling\n");
410 return;
411 }
412
413
414 if (tps65218_voltage_update(TPS65218_DCDC1,
415 TPS65218_DCDC_VOLT_SEL_1100MV)) {
416 printf("%s failure\n", __func__);
417 return;
418 }
419
420
421 if (tps65218_voltage_update(TPS65218_DCDC2, mpu_vdd)) {
422 printf("%s failure\n", __func__);
423 return;
424 }
425
426
427 if (tps65218_voltage_update(TPS65218_DCDC3,
428 TPS65218_DCDC3_VOLT_SEL_1350MV)) {
429 printf("%s failure\n", __func__);
430 return;
431 }
432}
433
434void scale_vcores_idk(u32 m)
435{
436 int mpu_vdd;
437
438 if (i2c_probe(TPS62362_I2C_ADDR))
439 return;
440
441 switch (m) {
442 case 1000:
443 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV;
444 break;
445 case 800:
446 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1260MV;
447 break;
448 case 720:
449 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1200MV;
450 break;
451 case 600:
452 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1100MV;
453 break;
454 case 300:
455 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV;
456 break;
457 default:
458 puts("Unknown MPU clock, not scaling\n");
459 return;
460 }
461
462
463 if (tps62362_voltage_update(TPS62362_SET3, mpu_vdd)) {
464 printf("%s failure\n", __func__);
465 return;
466 }
467}
468
469void gpi2c_init(void)
470{
471
472 static bool first_time = true;
473
474 if (first_time) {
475 enable_i2c0_pin_mux();
476 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED,
477 CONFIG_SYS_OMAP24_I2C_SLAVE);
478 first_time = false;
479 }
480}
481
482void scale_vcores(void)
483{
484 const struct dpll_params *mpu_params;
485
486
487 gpi2c_init();
488
489
490 mpu_params = get_dpll_mpu_params();
491
492 if (board_is_idk())
493 scale_vcores_idk(mpu_params->m);
494 else
495 scale_vcores_generic(mpu_params->m);
496}
497
498void set_uart_mux_conf(void)
499{
500 enable_uart0_pin_mux();
501}
502
503void set_mux_conf_regs(void)
504{
505 enable_board_pin_mux();
506}
507
508static void enable_vtt_regulator(void)
509{
510 u32 temp;
511
512
513 writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO5_BASE + OMAP_GPIO_CTRL);
514
515
516 writel(GPIO_SETDATAOUT(7),
517 AM33XX_GPIO5_BASE + OMAP_GPIO_SETDATAOUT);
518 temp = readl(AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
519 temp = temp & ~(GPIO_OE_ENABLE(7));
520 writel(temp, AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
521}
522
523void sdram_init(void)
524{
525
526
527
528
529
530 if (board_is_eposevm()) {
531 config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0);
532 } else if (board_is_evm_14_or_later()) {
533 enable_vtt_regulator();
534 config_ddr(0, &ioregs_ddr3, NULL, NULL,
535 &ddr3_emif_regs_400Mhz_production, 0);
536 } else if (board_is_evm_12_or_later()) {
537 enable_vtt_regulator();
538 config_ddr(0, &ioregs_ddr3, NULL, NULL,
539 &ddr3_emif_regs_400Mhz_beta, 0);
540 } else if (board_is_evm()) {
541 enable_vtt_regulator();
542 config_ddr(0, &ioregs_ddr3, NULL, NULL,
543 &ddr3_emif_regs_400Mhz, 0);
544 } else if (board_is_sk()) {
545 config_ddr(400, &ioregs_ddr3, NULL, NULL,
546 &ddr3_sk_emif_regs_400Mhz, 0);
547 } else if (board_is_idk()) {
548 config_ddr(400, &ioregs_ddr3, NULL, NULL,
549 &ddr3_idk_emif_regs_400Mhz, 0);
550 }
551}
552#endif
553
554
555int power_init_board(void)
556{
557 struct pmic *p;
558
559 if (board_is_idk()) {
560 power_tps62362_init(I2C_PMIC);
561 p = pmic_get("TPS62362");
562 if (p && !pmic_probe(p))
563 puts("PMIC: TPS62362\n");
564 } else {
565 power_tps65218_init(I2C_PMIC);
566 p = pmic_get("TPS65218_PMIC");
567 if (p && !pmic_probe(p))
568 puts("PMIC: TPS65218\n");
569 }
570
571 return 0;
572}
573
574int board_init(void)
575{
576 struct l3f_cfg_bwlimiter *bwlimiter = (struct l3f_cfg_bwlimiter *)L3F_CFG_BWLIMITER;
577 u32 mreqprio_0, mreqprio_1, modena_init0_bw_fractional,
578 modena_init0_bw_integer, modena_init0_watermark_0;
579
580 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
581 gpmc_init();
582
583
584 mreqprio_0 = readl(&cdev->mreqprio_0) & MREQPRIO_0_SAB_INIT1_MASK &
585 MREQPRIO_0_SAB_INIT0_MASK;
586
587 mreqprio_1 = readl(&cdev->mreqprio_1) & MREQPRIO_1_DSS_MASK;
588
589 modena_init0_bw_fractional = readl(&bwlimiter->modena_init0_bw_fractional) &
590 BW_LIMITER_BW_FRAC_MASK;
591
592 modena_init0_bw_integer = readl(&bwlimiter->modena_init0_bw_integer) &
593 BW_LIMITER_BW_INT_MASK;
594
595 modena_init0_watermark_0 = readl(&bwlimiter->modena_init0_watermark_0) &
596 BW_LIMITER_BW_WATERMARK_MASK;
597
598
599 mreqprio_0 |= 0x77;
600
601
602
603
604
605 modena_init0_bw_fractional |= 0x10;
606 modena_init0_bw_integer |= 0x3;
607
608 writel(mreqprio_0, &cdev->mreqprio_0);
609 writel(mreqprio_1, &cdev->mreqprio_1);
610
611 writel(modena_init0_bw_fractional, &bwlimiter->modena_init0_bw_fractional);
612 writel(modena_init0_bw_integer, &bwlimiter->modena_init0_bw_integer);
613 writel(modena_init0_watermark_0, &bwlimiter->modena_init0_watermark_0);
614
615 return 0;
616}
617
618#ifdef CONFIG_BOARD_LATE_INIT
619int board_late_init(void)
620{
621#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
622 set_board_info_env(NULL);
623
624
625
626
627
628 if (get_device_type() == HS_DEVICE)
629 setenv("boot_fit", "1");
630#endif
631 return 0;
632}
633#endif
634
635#ifdef CONFIG_USB_DWC3
636static struct dwc3_device usb_otg_ss1 = {
637 .maximum_speed = USB_SPEED_HIGH,
638 .base = USB_OTG_SS1_BASE,
639 .tx_fifo_resize = false,
640 .index = 0,
641};
642
643static struct dwc3_omap_device usb_otg_ss1_glue = {
644 .base = (void *)USB_OTG_SS1_GLUE_BASE,
645 .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
646 .index = 0,
647};
648
649static struct ti_usb_phy_device usb_phy1_device = {
650 .usb2_phy_power = (void *)USB2_PHY1_POWER,
651 .index = 0,
652};
653
654static struct dwc3_device usb_otg_ss2 = {
655 .maximum_speed = USB_SPEED_HIGH,
656 .base = USB_OTG_SS2_BASE,
657 .tx_fifo_resize = false,
658 .index = 1,
659};
660
661static struct dwc3_omap_device usb_otg_ss2_glue = {
662 .base = (void *)USB_OTG_SS2_GLUE_BASE,
663 .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
664 .index = 1,
665};
666
667static struct ti_usb_phy_device usb_phy2_device = {
668 .usb2_phy_power = (void *)USB2_PHY2_POWER,
669 .index = 1,
670};
671
672int usb_gadget_handle_interrupts(int index)
673{
674 u32 status;
675
676 status = dwc3_omap_uboot_interrupt_status(index);
677 if (status)
678 dwc3_uboot_handle_interrupt(index);
679
680 return 0;
681}
682#endif
683
684#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
685int omap_xhci_board_usb_init(int index, enum usb_init_type init)
686{
687 enable_usb_clocks(index);
688#ifdef CONFIG_USB_DWC3
689 switch (index) {
690 case 0:
691 if (init == USB_INIT_DEVICE) {
692 usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL;
693 usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
694 dwc3_omap_uboot_init(&usb_otg_ss1_glue);
695 ti_usb_phy_uboot_init(&usb_phy1_device);
696 dwc3_uboot_init(&usb_otg_ss1);
697 }
698 break;
699 case 1:
700 if (init == USB_INIT_DEVICE) {
701 usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
702 usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
703 ti_usb_phy_uboot_init(&usb_phy2_device);
704 dwc3_omap_uboot_init(&usb_otg_ss2_glue);
705 dwc3_uboot_init(&usb_otg_ss2);
706 }
707 break;
708 default:
709 printf("Invalid Controller Index\n");
710 }
711#endif
712
713 return 0;
714}
715
716int omap_xhci_board_usb_cleanup(int index, enum usb_init_type init)
717{
718#ifdef CONFIG_USB_DWC3
719 switch (index) {
720 case 0:
721 case 1:
722 if (init == USB_INIT_DEVICE) {
723 ti_usb_phy_uboot_exit(index);
724 dwc3_uboot_exit(index);
725 dwc3_omap_uboot_exit(index);
726 }
727 break;
728 default:
729 printf("Invalid Controller Index\n");
730 }
731#endif
732 disable_usb_clocks(index);
733
734 return 0;
735}
736#endif
737
738#ifdef CONFIG_DRIVER_TI_CPSW
739
740static void cpsw_control(int enabled)
741{
742
743 return;
744}
745
746static struct cpsw_slave_data cpsw_slaves[] = {
747 {
748 .slave_reg_ofs = 0x208,
749 .sliver_reg_ofs = 0xd80,
750 .phy_addr = 16,
751 },
752 {
753 .slave_reg_ofs = 0x308,
754 .sliver_reg_ofs = 0xdc0,
755 .phy_addr = 1,
756 },
757};
758
759static struct cpsw_platform_data cpsw_data = {
760 .mdio_base = CPSW_MDIO_BASE,
761 .cpsw_base = CPSW_BASE,
762 .mdio_div = 0xff,
763 .channels = 8,
764 .cpdma_reg_ofs = 0x800,
765 .slaves = 1,
766 .slave_data = cpsw_slaves,
767 .ale_reg_ofs = 0xd00,
768 .ale_entries = 1024,
769 .host_port_reg_ofs = 0x108,
770 .hw_stats_reg_ofs = 0x900,
771 .bd_ram_ofs = 0x2000,
772 .mac_control = (1 << 5),
773 .control = cpsw_control,
774 .host_port_num = 0,
775 .version = CPSW_CTRL_VERSION_2,
776};
777
778int board_eth_init(bd_t *bis)
779{
780 int rv;
781 uint8_t mac_addr[6];
782 uint32_t mac_hi, mac_lo;
783
784
785 mac_lo = readl(&cdev->macid0l);
786 mac_hi = readl(&cdev->macid0h);
787 mac_addr[0] = mac_hi & 0xFF;
788 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
789 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
790 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
791 mac_addr[4] = mac_lo & 0xFF;
792 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
793
794 if (!getenv("ethaddr")) {
795 puts("<ethaddr> not set. Validating first E-fuse MAC\n");
796 if (is_valid_ethaddr(mac_addr))
797 eth_setenv_enetaddr("ethaddr", mac_addr);
798 }
799
800 mac_lo = readl(&cdev->macid1l);
801 mac_hi = readl(&cdev->macid1h);
802 mac_addr[0] = mac_hi & 0xFF;
803 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
804 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
805 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
806 mac_addr[4] = mac_lo & 0xFF;
807 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
808
809 if (!getenv("eth1addr")) {
810 if (is_valid_ethaddr(mac_addr))
811 eth_setenv_enetaddr("eth1addr", mac_addr);
812 }
813
814 if (board_is_eposevm()) {
815 writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
816 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;
817 cpsw_slaves[0].phy_addr = 16;
818 } else if (board_is_sk()) {
819 writel(RGMII_MODE_ENABLE, &cdev->miisel);
820 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
821 cpsw_slaves[0].phy_addr = 4;
822 cpsw_slaves[1].phy_addr = 5;
823 } else if (board_is_idk()) {
824 writel(RGMII_MODE_ENABLE, &cdev->miisel);
825 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
826 cpsw_slaves[0].phy_addr = 0;
827 } else {
828 writel(RGMII_MODE_ENABLE, &cdev->miisel);
829 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
830 cpsw_slaves[0].phy_addr = 0;
831 }
832
833 rv = cpsw_register(&cpsw_data);
834 if (rv < 0)
835 printf("Error %d registering CPSW switch\n", rv);
836
837 return rv;
838}
839#endif
840
841#ifdef CONFIG_SPL_LOAD_FIT
842int board_fit_config_name_match(const char *name)
843{
844 if (board_is_evm() && !strcmp(name, "am437x-gp-evm"))
845 return 0;
846 else if (board_is_sk() && !strcmp(name, "am437x-sk-evm"))
847 return 0;
848 else if (board_is_eposevm() && !strcmp(name, "am43x-epos-evm"))
849 return 0;
850 else if (board_is_idk() && !strcmp(name, "am437x-idk-evm"))
851 return 0;
852 else
853 return -1;
854}
855#endif
856
857#ifdef CONFIG_TI_SECURE_DEVICE
858void board_fit_image_post_process(void **p_image, size_t *p_size)
859{
860 secure_boot_verify_image(p_image, p_size);
861}
862#endif
863
