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11#include <common.h>
12#include <errno.h>
13#include <libfdt.h>
14#include <spl.h>
15#include <asm/arch/cpu.h>
16#include <asm/arch/hardware.h>
17#include <asm/arch/omap.h>
18#include <asm/arch/ddr_defs.h>
19#include <asm/arch/clock.h>
20#include <asm/arch/gpio.h>
21#include <asm/arch/mmc_host_def.h>
22#include <asm/arch/sys_proto.h>
23#include <asm/arch/mem.h>
24#include <asm/arch/mux.h>
25#include <asm/io.h>
26#include <asm/emif.h>
27#include <asm/gpio.h>
28#include <i2c.h>
29#include <miiphy.h>
30#include <cpsw.h>
31#include <power/tps65217.h>
32#include <power/tps65910.h>
33#include <environment.h>
34#include <watchdog.h>
35#include "board.h"
36
37DECLARE_GLOBAL_DATA_PTR;
38
39
40#define GPIO_DDR_VTT_EN 7
41#define DIP_S1 44
42#define MPCIE_SW 100
43
44static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
45
46static int baltos_set_console(void)
47{
48 int val, i, dips = 0;
49 char buf[7];
50
51 for (i = 0; i < 4; i++) {
52 sprintf(buf, "dip_s%d", i + 1);
53
54 if (gpio_request(DIP_S1 + i, buf)) {
55 printf("failed to export GPIO %d\n", DIP_S1 + i);
56 return 0;
57 }
58
59 if (gpio_direction_input(DIP_S1 + i)) {
60 printf("failed to set GPIO %d direction\n", DIP_S1 + i);
61 return 0;
62 }
63
64 val = gpio_get_value(DIP_S1 + i);
65 dips |= val << i;
66 }
67
68 printf("DIPs: 0x%1x\n", (~dips) & 0xf);
69
70 if ((dips & 0xf) == 0xe)
71 setenv("console", "ttyUSB0,115200n8");
72
73 return 0;
74}
75
76static int read_eeprom(BSP_VS_HWPARAM *header)
77{
78 i2c_set_bus_num(1);
79
80
81 if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
82 puts("Could not probe the EEPROM; something fundamentally "
83 "wrong on the I2C bus.\n");
84 return -ENODEV;
85 }
86
87
88 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
89 sizeof(BSP_VS_HWPARAM))) {
90 puts("Could not read the EEPROM; something fundamentally"
91 " wrong on the I2C bus.\n");
92 return -EIO;
93 }
94
95 if (header->Magic != 0xDEADBEEF) {
96
97 printf("Incorrect magic number (0x%x) in EEPROM\n",
98 header->Magic);
99
100
101 header->SystemId = 211;
102 header->MAC1[0] = 0x00;
103 header->MAC1[1] = 0x00;
104 header->MAC1[2] = 0x00;
105 header->MAC1[3] = 0x00;
106 header->MAC1[4] = 0x00;
107 header->MAC1[5] = 0x01;
108
109 header->MAC2[0] = 0x00;
110 header->MAC2[1] = 0x00;
111 header->MAC2[2] = 0x00;
112 header->MAC2[3] = 0x00;
113 header->MAC2[4] = 0x00;
114 header->MAC2[5] = 0x02;
115
116 header->MAC3[0] = 0x00;
117 header->MAC3[1] = 0x00;
118 header->MAC3[2] = 0x00;
119 header->MAC3[3] = 0x00;
120 header->MAC3[4] = 0x00;
121 header->MAC3[5] = 0x03;
122 }
123
124 return 0;
125}
126
127#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
128
129static const struct ddr_data ddr3_baltos_data = {
130 .datardsratio0 = MT41K256M16HA125E_RD_DQS,
131 .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
132 .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
133 .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
134};
135
136static const struct cmd_control ddr3_baltos_cmd_ctrl_data = {
137 .cmd0csratio = MT41K256M16HA125E_RATIO,
138 .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
139
140 .cmd1csratio = MT41K256M16HA125E_RATIO,
141 .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
142
143 .cmd2csratio = MT41K256M16HA125E_RATIO,
144 .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
145};
146
147static struct emif_regs ddr3_baltos_emif_reg_data = {
148 .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
149 .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
150 .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
151 .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
152 .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
153 .zq_config = MT41K256M16HA125E_ZQ_CFG,
154 .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
155};
156
157#ifdef CONFIG_SPL_OS_BOOT
158int spl_start_uboot(void)
159{
160
161 return (serial_tstc() && serial_getc() == 'c');
162}
163#endif
164
165#define OSC (V_OSCK/1000000)
166const struct dpll_params dpll_ddr = {
167 266, OSC-1, 1, -1, -1, -1, -1};
168const struct dpll_params dpll_ddr_evm_sk = {
169 303, OSC-1, 1, -1, -1, -1, -1};
170const struct dpll_params dpll_ddr_baltos = {
171 400, OSC-1, 1, -1, -1, -1, -1};
172
173void am33xx_spl_board_init(void)
174{
175 int mpu_vdd;
176 int sil_rev;
177
178
179 dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
180
181
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183
184
185
186
187 i2c_set_bus_num(1);
188
189 printf("I2C speed: %d Hz\n", CONFIG_SYS_OMAP24_I2C_SPEED);
190
191 if (i2c_probe(TPS65910_CTRL_I2C_ADDR)) {
192 puts("i2c: cannot access TPS65910\n");
193 return;
194 }
195
196
197
198
199
200 sil_rev = readl(&cdev->deviceid) >> 28;
201 mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev,
202 dpll_mpu_opp100.m);
203
204
205 tps65910_set_i2c_control();
206
207
208 if (tps65910_voltage_update(MPU, mpu_vdd))
209 return;
210
211
212 if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3))
213 return;
214
215
216 do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
217
218
219 do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
220
221 writel(0x000010ff, PRM_DEVICE_INST + 4);
222}
223
224const struct dpll_params *get_dpll_ddr_params(void)
225{
226 enable_i2c1_pin_mux();
227 i2c_set_bus_num(1);
228
229 return &dpll_ddr_baltos;
230}
231
232void set_uart_mux_conf(void)
233{
234 enable_uart0_pin_mux();
235}
236
237void set_mux_conf_regs(void)
238{
239 enable_board_pin_mux();
240}
241
242const struct ctrl_ioregs ioregs_baltos = {
243 .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
244 .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
245 .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
246 .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
247 .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
248};
249
250void sdram_init(void)
251{
252 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
253 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
254
255 config_ddr(400, &ioregs_baltos,
256 &ddr3_baltos_data,
257 &ddr3_baltos_cmd_ctrl_data,
258 &ddr3_baltos_emif_reg_data, 0);
259}
260#endif
261
262
263
264
265int board_init(void)
266{
267#if defined(CONFIG_HW_WATCHDOG)
268 hw_watchdog_init();
269#endif
270
271 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
272#if defined(CONFIG_NOR) || defined(CONFIG_NAND)
273 gpmc_init();
274#endif
275 return 0;
276}
277
278int ft_board_setup(void *blob, bd_t *bd)
279{
280 int node, ret;
281 unsigned char mac_addr[6];
282 BSP_VS_HWPARAM header;
283
284
285 if (read_eeprom(&header))
286 return 0;
287
288
289 mac_addr[0] = header.MAC1[0];
290 mac_addr[1] = header.MAC1[1];
291 mac_addr[2] = header.MAC1[2];
292 mac_addr[3] = header.MAC1[3];
293 mac_addr[4] = header.MAC1[4];
294 mac_addr[5] = header.MAC1[5];
295
296
297 node = fdt_path_offset(blob, "/ocp/ethernet/slave@4a100200");
298 if (node < 0) {
299 printf("no /soc/fman/ethernet path offset\n");
300 return -ENODEV;
301 }
302
303 ret = fdt_setprop(blob, node, "mac-address", &mac_addr, 6);
304 if (ret) {
305 printf("error setting local-mac-address property\n");
306 return -ENODEV;
307 }
308
309
310 mac_addr[0] = header.MAC2[0];
311 mac_addr[1] = header.MAC2[1];
312 mac_addr[2] = header.MAC2[2];
313 mac_addr[3] = header.MAC2[3];
314 mac_addr[4] = header.MAC2[4];
315 mac_addr[5] = header.MAC2[5];
316
317 node = fdt_path_offset(blob, "/ocp/ethernet/slave@4a100300");
318 if (node < 0) {
319 printf("no /soc/fman/ethernet path offset\n");
320 return -ENODEV;
321 }
322
323 ret = fdt_setprop(blob, node, "mac-address", &mac_addr, 6);
324 if (ret) {
325 printf("error setting local-mac-address property\n");
326 return -ENODEV;
327 }
328
329 printf("\nFDT was successfully setup\n");
330
331 return 0;
332}
333
334static struct module_pin_mux pcie_sw_pin_mux[] = {
335 {OFFSET(mii1_rxdv), (MODE(7) | PULLUDEN )},
336 {-1},
337};
338
339static struct module_pin_mux dip_pin_mux[] = {
340 {OFFSET(gpmc_ad12), (MODE(7) | RXACTIVE )},
341 {OFFSET(gpmc_ad13), (MODE(7) | RXACTIVE )},
342 {OFFSET(gpmc_ad14), (MODE(7) | RXACTIVE )},
343 {OFFSET(gpmc_ad15), (MODE(7) | RXACTIVE )},
344 {-1},
345};
346
347#ifdef CONFIG_BOARD_LATE_INIT
348int board_late_init(void)
349{
350#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
351 BSP_VS_HWPARAM header;
352 char model[4];
353
354
355 if (read_eeprom(&header)) {
356 strcpy(model, "211");
357 } else {
358 sprintf(model, "%d", header.SystemId);
359 if (header.SystemId == 215) {
360 configure_module_pin_mux(dip_pin_mux);
361 baltos_set_console();
362 }
363 }
364
365
366 configure_module_pin_mux(pcie_sw_pin_mux);
367 if (gpio_request(MPCIE_SW, "mpcie_sw")) {
368 printf("failed to export GPIO %d\n", MPCIE_SW);
369 return -ENODEV;
370 }
371 if (gpio_direction_output(MPCIE_SW, 1)) {
372 printf("failed to set GPIO %d direction\n", MPCIE_SW);
373 return -ENODEV;
374 }
375
376 setenv("board_name", model);
377#endif
378
379 return 0;
380}
381#endif
382
383#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
384 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
385static void cpsw_control(int enabled)
386{
387
388
389 return;
390}
391
392static struct cpsw_slave_data cpsw_slaves[] = {
393 {
394 .slave_reg_ofs = 0x208,
395 .sliver_reg_ofs = 0xd80,
396 .phy_addr = 0,
397 },
398 {
399 .slave_reg_ofs = 0x308,
400 .sliver_reg_ofs = 0xdc0,
401 .phy_addr = 7,
402 },
403};
404
405static struct cpsw_platform_data cpsw_data = {
406 .mdio_base = CPSW_MDIO_BASE,
407 .cpsw_base = CPSW_BASE,
408 .mdio_div = 0xff,
409 .channels = 8,
410 .cpdma_reg_ofs = 0x800,
411 .slaves = 2,
412 .slave_data = cpsw_slaves,
413 .active_slave = 1,
414 .ale_reg_ofs = 0xd00,
415 .ale_entries = 1024,
416 .host_port_reg_ofs = 0x108,
417 .hw_stats_reg_ofs = 0x900,
418 .bd_ram_ofs = 0x2000,
419 .mac_control = (1 << 5),
420 .control = cpsw_control,
421 .host_port_num = 0,
422 .version = CPSW_CTRL_VERSION_2,
423};
424#endif
425
426#if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) \
427 && defined(CONFIG_SPL_BUILD)) || \
428 ((defined(CONFIG_DRIVER_TI_CPSW) || \
429 defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)) && \
430 !defined(CONFIG_SPL_BUILD))
431int board_eth_init(bd_t *bis)
432{
433 int rv, n = 0;
434 uint8_t mac_addr[6];
435 uint32_t mac_hi, mac_lo;
436
437
438
439
440
441
442
443
444
445 mac_lo = readl(&cdev->macid1l);
446 mac_hi = readl(&cdev->macid1h);
447 mac_addr[0] = mac_hi & 0xFF;
448 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
449 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
450 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
451 mac_addr[4] = mac_lo & 0xFF;
452 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
453
454#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
455 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
456 if (!getenv("ethaddr")) {
457 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
458
459 if (is_valid_ethaddr(mac_addr))
460 eth_setenv_enetaddr("ethaddr", mac_addr);
461 }
462
463#ifdef CONFIG_DRIVER_TI_CPSW
464 writel((GMII1_SEL_RMII | GMII2_SEL_RGMII | RGMII2_IDMODE), &cdev->miisel);
465 cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII;
466 rv = cpsw_register(&cpsw_data);
467 if (rv < 0)
468 printf("Error %d registering CPSW switch\n", rv);
469 else
470 n += rv;
471#endif
472
473
474
475
476
477
478
479
480#define AR8051_PHY_DEBUG_ADDR_REG 0x1d
481#define AR8051_PHY_DEBUG_DATA_REG 0x1e
482#define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5
483#define AR8051_RGMII_TX_CLK_DLY 0x100
484 const char *devname;
485 devname = miiphy_get_current_dev();
486
487 miiphy_write(devname, 0x7, AR8051_PHY_DEBUG_ADDR_REG,
488 AR8051_DEBUG_RGMII_CLK_DLY_REG);
489 miiphy_write(devname, 0x7, AR8051_PHY_DEBUG_DATA_REG,
490 AR8051_RGMII_TX_CLK_DLY);
491#endif
492 return n;
493}
494#endif
495
